ISE 14.7 std_logic is not declared

Question

I have installed ISE 14.7 from CD came with Artix 7 AC701 board.
When i synthesize i get the following error. 
ERROR:HDLCompiler:69 - "D:\Xilinx_Projects\fsm_test\test.vhd" Line 53: <std_logic> is not declared
Any solutions?

Answer 1

tanishaa122 wrote:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
package Convolution_pkg IS
TYPE real_vector is ARRAY(integer RANGE <>) OF real;
end;
use work.Convolution_pkg.ALL;
entity convolution is
    port ( x:in STD_LOGIC_VECTOR (0 to 3);
    h:in STD_LOGIC_VECTOR (0 to 1);
    y:out STD_LOGIC_VECTOR (0 to 4));
end convolution;
architecture Behavioral of convolution is
BEGIN
    process (x,h)
        variable sum :real := 0.0;
        variable temp :integer := 0;
    begin
        for k in y'range loop
            sum:=0.0;
            for n in h'range loop
                temp := k-n;
                if temp >= 0 then
                    sum := sum + h(n)*x(temp);
                end if;
            end loop;
            y(k) <= sum ;
        end loop;
    end process;
end Behavioral;
 in the following code i am getting the below errors:
 Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "E:/newcovolution/convolution.xst" -ofn "E:/newcovolution/convolution.syr"
Reading design: convolution.prj
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "E:\newcovolution\codecov.vhd" into library work
Parsing package <Convolution_pkg>.
Parsing entity <convolution>.
ERROR:HDLCompiler:69 - "E:\newcovolution\codecov.vhd" Line 14: <std_logic_vector> is not declared.
ERROR:HDLCompiler:69 - "E:\newcovolution\codecov.vhd" Line 15: <std_logic_vector> is not declared.
VHDL file E:\newcovolution\codecov.vhd ignored due to errors
You must always put the library use clauses at the start of every design unit.
Putting them at the start of a source file, when that source file includes more than one design unit, is not sufficient.
It is generally recommended to have only one design unit (entity, package, whatever) per file, and that file's name should be the same as the design unit's.
And after you fix that, how do you propose to assign a real value to a std_logic_vector?