Multiple clock domains each with clock mulitplexing. Solve warning (Place 30-568])

Question

My design can be partitioned in several clock regions (up to 20 for now). In each region I've instantiated a PLL and each PLL generates 4 clocks. I need to multiplex these 4 clocks per each region and to clock gate the output based on a signal in the fabric logic.
I know the a proper way of doing it would be to use 3 BUFGMUX components followed by a BUFGCE, however this has issues:
1) Even if I have a V2000 Virtex7 FPGA, I can only use up to 32 BUFGs because of the placement constraints.
2) Assuming I could give up and reduce the number of clock regions, it's impossible to place all 4 BUFGs in adjacent sites, therefore implementation fails unless I specify DEDICATED_CLOCK_ROUTE FALSE. I would prefer avoiding this option, because the design is fairly complex and Vivado struggles to meet timing already.
I tried to multiplex the the first level of clocks with the fabric logic (simple MUXes in RTL) and then to multiplex them with a BUFGCTRL.
Finally I used a BUFGCE to clock gate part of the logic. This reduces the number of BUFG per region to 2 (still not enough, but better than 4), the logic has no glitches on the output clock and the scheme looks like the following:
clk0 _
         |_ 
          _ RTL_MUX (LUT)___
clk1 _|                                    |
                                               |__
clk2 _                                       __BUFGCTRL____BUFGCE_______logic
         |_                                    |                           |
          _ RTL_MUX (LUT)____|                           |__clock_gating/selection_logic
clk3 _| 
This attempt worked with a portion of the design and everything runs correctly. However when I instantiate the entire design (rougtly 50% occupation on the V2000), Vivado is unable to fix hold violations.
In addition, with both the full design and the smaller portion, I still warnings, which I don't know how to resolve. Maybe if I could fix those, I would have more chances to get a working design.
This is the warning I'm getting:
[Place 30-568] A LUT 'clkmux_3/bufgctrl_1_i_2' is driving clock pin of 24 registers. This could lead to large hold time violations. First few involved registers are:
I checked the schematic and the clocks multiplexed with the LUTs go straight to the BUFGCTRL, which is the one driving the registers listed in the warming. Does this mean that even if I use a BUFG, Vivado is still detecting that the clock originates from an LUT (the input to the BUFG)? Do you know a workaround?
Thank you in advance. Kind regards.
Paolo

Answer 1

Hi,
Ideally what you are trying to do is using gated clocks. Clock should in general not be gated through LUT's or fabric logic. You should use buffers to do that. However in your case, considering you have taken care of the hold violations and the timing, you can safely ignore these warnings. This warnings just warns you about the clock gating throught he LUT's which might affect the device timing. Write proper timing constraints and make sure you meet timing. That shoud do.