PXIe-5170R decimation/filtering using design libraries?

Hi,
NOTE: This question mentions FPGA but users of the 5170R who haven't touched the FPGA may be able to help.
I'm looking to develop an application using the 5170R oscilloscope design libraries, and although I'm hoping to achieve my aims without modifying the FPGA side code, I did take a peek out of curiosity.
To stream the number of channels I want I will probably end up having to set a decimation factor of greater than one (set on the host VI, sent to the FPGA to set the decimation between the sample loop and the output stream), however the decimator in the FPGA specifically states that it provides no anti-aliasing filter, so my question is, is this design library not fit for 'out of the box' use at non-unity decimation factors, or is there something I'm not seeing, like a setting for some internal device hardware filter on the acquisition side of the unit?
For users without FPGA experience, if you have used a decimation factor>1, was there aliasing on your output signal?
Thanks
Lee

Hi There ToeCutter!
I've found this which might be of help, please take a look through and let me know!
http://www.ni.com/white-paper/11342/en/#toc3
Kind Regards,

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