Trigger oscilloscope on specific write to I2C EEPROM?
My only experience with hardware and LabVIEW is controlling instruments using visa. I have an I2C problem I am trying to debug and maybe someone knows if NI makes hardware that will work for me.
I want to trigger an oscilloscope on an I2C write to a specific 24C32 EEPROM address so I can look at the activity preceding that. Could one of the DAQ cards do this and would I need LV Real Time?
I have a Total Phase I2C monitor and I can log the transactions. But some of the transactions are corrupt and there are mysterious erroneous writes to a few different EEPROM memory locations. Interestingly it writes the address of the I2C device to these locations. So I need to look at the waveform immediately preceding one of these unexplained writes.
Maybe the DAQ card can be the scope if I use analog inputs. If I capture the clock and data is there a vi that already exists that will decode the bit stream?
The way I might go about this is with a PIC microcontroller. I can write a program for that which I can send commands to through LabVIEW. I could tell the PIC to make a digital line go high when it sees a particular bit stream and use that to trigger the scope.
=====================
LabVIEW 2012
Please use the forum post located here.
Kareem W.
National Instruments
Web Product Manager
Similar Messages
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Trigger oscilloscope on specific I2C write?
Apologies for cross posting this from the Automotive and Embedded forum but there just doesn't seem to be much "traffic" there (no pun intended) I did a search and only found about four posts that even mention I2C. Most are about CAN.
My only experience with hardware and LabVIEW is controlling instruments using visa. I have an I2C problem I am trying to debug and maybe someone knows if NI makes hardware that will work for me.
I want to trigger an oscilloscope on an I2C write to a specific 24C32 EEPROM address so I can look at the waveform preceding that. Could one of the DAQ cards do this and would I need LV Real Time?
I have a Total Phase I2C monitor and I can log the transactions. But some of the transactions are corrupt and there are mysterious erroneous writes to a few different EEPROM memory locations. Interestingly it writes the address of the I2C device to these locations. So I need to look at the waveform immediately preceding one of these unexplained writes.
Maybe the DAQ card can be the scope if I use analog inputs. If I capture the clock and data is there a vi that already exists that will decode the bit stream?
The way I might go about this is with a PIC microcontroller. I can write a program for that which I can send commands to through LabVIEW. I could tell the PIC to make a digital line go high when it sees a particular bit stream and use that to trigger the scope.
What would you do?
=====================
LabVIEW 2012On a specific write
That makes it more challenging and could be a pile of work used just one time.
A continuous acq at a high rate to catch the issue then go back through it manually can get you there but a lot of manual scrolling and decyphering.
I think there are some FPGA examples available that support low levl protocols. You may be able to start with there work, not sure.
I'll process this challeng in the background and if I have more ideas I'll share.
Ben
Ben Rayner
I am currently active on.. MainStream Preppers
Rayner's Ridge is under construction -
SpbTestTool sample / I2C EEPROM / OnPrepareHardware / WdfCmResourceListGetCount == 0
I am using the SpbTestTool sample to support an I2C EEPROM. I have noticed that in OnPrepareHardware the WdfCmResourceListGetCount returns 0.
The sample at this point does the following in device.cpp:
// An SPB resource is required.
if (fSpbResourceFound == FALSE)
status = STATUS_NOT_FOUND;
Trace(
TRACE_LEVEL_ERROR,
TRACE_FLAG_WDFLOADING,
"SPB resource not found - %!STATUS!",
status);
which causes OnPrepareHardware to return STATUS_NOT_FOUND and the driver then fails to load.
QUESTION Should the EEPROM have resources or is this a bug in the sample driver? Other thoughts?Here is the PCI debug output right before the driver loads. Are there any debug tips for digging into this further?
3: kd> !pcitree
Bus 0x0 (FDO Ext ffffe00183817190)
(d=0, f=0) 80860f00 devext 0xffffe001838131b0 devstack 0xffffe00183813060 0600 Bridge/HOST to PCI
(d=2, f=0) 80860f31 devext 0xffffe001838139d0 devstack 0xffffe00183813880 0300 Display Controller/VGA
(d=13, f=0) 80860f23 devext 0xffffe001838121b0 devstack 0xffffe00183812060 0106 Mass Storage Controller/Unknown Sub Class
(d=14, f=0) 80860f35 devext 0xffffe001838129d0 devstack 0xffffe00183812880 0c03 Serial Bus Controller/USB
(d=1a, f=0) 80860f18 devext 0xffffe001838111b0 devstack 0xffffe00183811060 1080 Unknown Base Class/Unknown Sub Class
(d=1b, f=0) 80860f04 devext 0xffffe001838119d0 devstack 0xffffe00183811880 0403 Multimedia Device/Unknown Sub Class
(d=1c, f=0) 80860f48 devext 0xffffe001838101b0 devstack 0xffffe00183810060 0604 Bridge/PCI to PCI
Bus 0x1 (FDO Ext ffffe0018380bcf0)
No devices have been enumerated on this bus.
(d=1c, f=1) 80860f4a devext 0xffffe001838109d0 devstack 0xffffe00183810880 0604 Bridge/PCI to PCI
Bus 0x2 (FDO Ext ffffe00183808a30)
No devices have been enumerated on this bus.
(d=1c, f=2) 80860f4c devext 0xffffe0018380f1b0 devstack 0xffffe0018380f060 0604 Bridge/PCI to PCI
Bus 0x3 (FDO Ext ffffe00183807cf0)
No devices have been enumerated on this bus.
(d=1c, f=3) 80860f4e devext 0xffffe0018380f9d0 devstack 0xffffe0018380f880 0604 Bridge/PCI to PCI
Bus 0x4 (FDO Ext ffffe00183806cf0)
(d=0, f=0) 80861533 devext 0xffffe001839526b0 devstack 0xffffe00183952560 0200 Network Controller/Ethernet
(d=1f, f=0) 80860f1c devext 0xffffe0018380e1b0 devstack 0xffffe0018380e060 0601 Bridge/PCI to ISA
(d=1f, f=3) 80860f12 devext 0xffffe0018380e9d0 devstack 0xffffe0018380e880 0c05 Serial Bus Controller/Unknown Sub Class
Total PCI Root busses processed = 1
Total PCI Segments processed = 1
3: kd> !pci 144
PCI Configuration Space (Segment:0000 Bus:00 Device:00 Function:00)
Common Header:
00: VendorID 8086 Intel Corporation
02: DeviceID 0f00
04: Command 0007 IOSpaceEn MemSpaceEn BusInitiate
06: Status 0000
08: RevisionID 11
09: ProgIF 00
0a: SubClass 00 Host Bridge
0b: BaseClass 06 Bridge Device
0c: CacheLineSize 0000
0d: LatencyTimer 00
0e: HeaderType 00
0f: BIST 00
10: BAR0 00000000
14: BAR1 00000000
18: BAR2 00000000
1c: BAR3 00000000
20: BAR4 00000000
24: BAR5 00000000
28: CBCISPtr 00000000
2c: SubSysVenID 8086
2e: SubSysID 0f31
30: ROMBAR 00000000
34: CapPtr 00
3c: IntLine 00
3d: IntPin 00
3e: MinGnt 00
3f: MaxLat 00
Device Private:
40: 00000000 00000000 00000000 00000000
50: 00000000 00000000 00000000 00000000
60: 00000000 00000000 00000000 00000000
70: 00000000 00000000 00000000 00000000
80: 00000000 00000000 00000000 00000000
90: 00000000 00000000 00000000 00000000
a0: 00000000 00000000 00000000 00000000
b0: 00000000 00000000 00000000 00000000
c0: 00000000 00000000 00000000 00000000
d0: 00000000 00000000 00000000 00000000
e0: 00000000 00000000 00000000 00000000
f0: 00000066 00000000 00000000 00000000
01
PCI Configuration Space (Segment:0000 Bus:00 Device:02 Function:00)
Common Header:
00: VendorID 8086 Intel Corporation
02: DeviceID 0f31
04: Command 0407 IOSpaceEn MemSpaceEn BusInitiate InterruptDis
06: Status 0010 CapList
08: RevisionID 11
09: ProgIF 00 VGA
0a: SubClass 00 VGA Compatible Controller
0b: BaseClass 03 Display Controller
0c: CacheLineSize 0000
0d: LatencyTimer 00
0e: HeaderType 00
0f: BIST 00
10: BAR0 d0000000
14: BAR1 00000000
18: BAR2 c0000008
1c: BAR3 00000000
20: BAR4 0000e081
24: BAR5 00000000
28: CBCISPtr 00000000
2c: SubSysVenID 8086
2e: SubSysID 0f31
30: ROMBAR 00000000
34: CapPtr d0
3c: IntLine 0b
3d: IntPin 01
3e: MinGnt 00
3f: MaxLat 00
Device Private:
40: 00000000 00000000 00000000 00000000
50: 00000211 00000000 00000000 bb000001
60: 00020000 00000000 00000000 00000000
70: bae00001 00000007 00000000 00000000
80: 00000000 00000000 00000000 00000000
90: 0000b005 00000000 00000000 00000000
a0: 00000000 03060013 00000000 00000000
b0: 01070009 00000000 00000000 00000000
c0: 00000000 00000000 00000000 00000000
d0: 00229001 00000000 00000000 00000000
e0: 00008000 00000000 00000000 00000000
f0: 00000000 00000000 00010fd1 b9769018
Capabilities:
d0: CapID 01 PwrMgmt Capability
d1: NextPtr 90
d2: PwrMgmtCap 0022 DSI Version=2
d4: PwrMgmtCtrl 0000 DataScale:0 DataSel:0 D0
90: CapID 05 MSI Capability
91: NextPtr b0
92: MsgCtrl MultipleMsgEnable:0 (0x1) MultipleMsgCapable:0 (0x1)
94: MsgAddr 0
98: MsData 0
b0: CapID 09 Vendor Specific Capability
b1: NextPtr 00
12
PCI Configuration Space (Segment:0000 Bus:00 Device:13 Function:00)
Common Header:
00: VendorID 8086 Intel Corporation
02: DeviceID 0f23
04: Command 0007 IOSpaceEn MemSpaceEn BusInitiate
06: Status 02b0 CapList 66MHzCapable FB2BCapable DEVSELTiming:1
08: RevisionID 11
09: ProgIF 01
0a: SubClass 06
0b: BaseClass 01
0c: CacheLineSize 0000
0d: LatencyTimer 00
0e: HeaderType 00
0f: BIST 00
10: BAR0 0000e071
14: BAR1 0000e061
18: BAR2 0000e051
1c: BAR3 0000e041
20: BAR4 0000e021
24: BAR5 d0720000
28: CBCISPtr 00000000
2c: SubSysVenID 8086
2e: SubSysID 0f23
30: ROMBAR 00000000
34: CapPtr 80
3c: IntLine 13
3d: IntPin 01
3e: MinGnt 00
3f: MaxLat 00
Device Private:
40: 80008000 00000000 00000000 00000000
50: 00000000 00000000 00000000 00000000
60: 00000000 00000000 00000000 00000000
70: 4003a801 00000008 00000000 00000000
80: 00007005 00000000 00000000 00000000
90: 81010e60 3e000183 22dc0220 80007000
a0: 000000f4 00000000 00100012 00000048
b0: 03060013 00000000 00000000 00000000
c0: 00000000 00000000 00000000 00000000
d0: 00000000 00000000 00000000 00000000
e0: 00000000 00000000 00000000 00000000
f0: 00000000 00000000 01110f1a 00000000
Capabilities:
80: CapID 05 MSI Capability
81: NextPtr 70
82: MsgCtrl MultipleMsgEnable:0 (0x1) MultipleMsgCapable:0 (0x1)
84: MsgAddr 0
88: MsData 0
70: CapID 01 PwrMgmt Capability
71: NextPtr a8
72: PwrMgmtCap 4003 PMED3Hot Version=3
74: PwrMgmtCtrl 0008 DataScale:0 DataSel:0 D0
a8: CapID 12 Unknown Capability
a9: NextPtr 00
PCI Configuration Space (Segment:0000 Bus:00 Device:14 Function:00)
Common Header:
00: VendorID 8086 Intel Corporation
02: DeviceID 0f35
04: Command 0406 MemSpaceEn BusInitiate InterruptDis
06: Status 0290 CapList FB2BCapable DEVSELTiming:1
08: RevisionID 11
09: ProgIF 30
0a: SubClass 03
0b: BaseClass 0c
0c: CacheLineSize 0000
0d: LatencyTimer 00
0e: HeaderType 00
0f: BIST 00
10: BAR0 d0700004
14: BAR1 00000000
18: BAR2 00000000
1c: BAR3 00000000
20: BAR4 00000000
24: BAR5 00000000
28: CBCISPtr 00000000
2c: SubSysVenID 8086
2e: SubSysID 0f35
30: ROMBAR 00000000
34: CapPtr 70
3c: IntLine 00
3d: IntPin 01
3e: MinGnt 00
3f: MaxLat 00
Device Private:
40: 800401fd 83cfc68f 00000000 00000000
50: 0bce6e5f 00000000 00000000 00000000
60: 00002030 00000000 00000000 00000000
70: c1c28001 00000008 00000000 00000000
80: 00b70005 fee0f00c 00000000 000049b8
90: 00000000 00000000 00000000 00000000
a0: 00040100 00000000 00000000 00000000
b0: 0000008f 00000000 00000000 00000000
c0: 00000c03 00000000 00000001 00000000
d0: 0000003f 0000003f 00000001 00000001
e0: 00002c30 00000000 00000000 0000d8d8
f0: 00000000 00000000 01110f1a 00000000
Capabilities:
70: CapID 01 PwrMgmt Capability
71: NextPtr 80
72: PwrMgmtCap c1c2 PMED3Hot PMED3Cold Version=2
74: PwrMgmtCtrl 0008 DataScale:0 DataSel:0 D0
80: CapID 05 MSI Capability
81: NextPtr 00
82: MsgCtrl 64BitCapable MSIEnable MultipleMsgEnable:3 (0x8) MultipleMsgCapable:3 (0x8)
84: MsgAddr fee0f00c
88: MsgAddrHi 0
8c: MsData 49b8
19
PCI Configuration Space (Segment:0000 Bus:00 Device:1a Function:00)
Common Header:
00: VendorID 8086 Intel Corporation
02: DeviceID 0f18
04: Command 0106 MemSpaceEn BusInitiate SERREn
06: Status 0010 CapList
08: RevisionID 11
09: ProgIF 00
0a: SubClass 80 Other Encryption Controller
0b: BaseClass 10 Encryption Controller
0c: CacheLineSize 0010 BurstDisabled
0d: LatencyTimer 00
0e: HeaderType 00
0f: BIST 00
10: BAR0 d0500000
14: BAR1 d0400000
18: BAR2 00000000
1c: BAR3 00000000
20: BAR4 00000000
24: BAR5 00000000
28: CBCISPtr 00000000
2c: SubSysVenID 8086
2e: SubSysID 0f18
30: ROMBAR 00000000
34: CapPtr 80
3c: IntLine 0b
3d: IntPin 01
3e: MinGnt 00
3f: MaxLat 00
Device Private:
40: 1f0000d5 80004000 69000000 00000000
50: 0000000c 00000104 00000000 00000000
60: 10000000 00000001 00000000 00000000
70: 00000000 00000000 00000000 00000000
80: 4803a001 00000008 00000000 00000000
90: 00000000 00000000 00000000 00000000
a0: 00000005 00000000 00000000 00000000
b0: 80000000 00000000 00000000 00000000
c0: 00001009 bf000000 01000000 00000000
d0: 00003008 00000000 00000000 00000000
e0: 00000000 00000000 00000000 00000000
f0: 00000000 00000000 01110f1a 00000000
Capabilities:
80: CapID 01 PwrMgmt Capability
81: NextPtr a0
82: PwrMgmtCap 4803 PMED0 PMED3Hot Version=3
84: PwrMgmtCtrl 0008 DataScale:0 DataSel:0 D0
a0: CapID 05 MSI Capability
a1: NextPtr 00
a2: MsgCtrl MultipleMsgEnable:0 (0x1) MultipleMsgCapable:0 (0x1)
a4: MsgAddr 0
a8: MsData 0
PCI Configuration Space (Segment:0000 Bus:00 Device:1b Function:00)
Common Header:
00: VendorID 8086 Intel Corporation
02: DeviceID 0f04
04: Command 0006 MemSpaceEn BusInitiate
06: Status 0010 CapList
08: RevisionID 11
09: ProgIF 00
0a: SubClass 03
0b: BaseClass 04
0c: CacheLineSize 0010 BurstDisabled
0d: LatencyTimer 00
0e: HeaderType 00
0f: BIST 00
10: BAR0 d0710004
14: BAR1 00000000
18: BAR2 00000000
1c: BAR3 00000000
20: BAR4 00000000
24: BAR5 00000000
28: CBCISPtr 00000000
2c: SubSysVenID 8086
2e: SubSysID 7270
30: ROMBAR 00000000
34: CapPtr 50
3c: IntLine 16
3d: IntPin 01
3e: MinGnt 00
3f: MaxLat 00
Device Private:
40: 5d000001 ffffffff ffffffff 00000000
50: c8426001 00000000 ffffffff ffffffff
60: 00800005 00000000 00000000 00000000
70: 00910010 10000000 00100800 ffffffff
80: ffffffff ffffffff ffffffff ffffffff
90: ffffffff ffffffff ffffffff ffffffff
a0: ffffffff ffffffff ffffffff ffffffff
b0: ffffffff ffffffff ffffffff ffffffff
c0: 01e00400 4c002402 82a30000 02330010
d0: 02a30c00 02330010 ffffffff ffffffff
e0: ffffffff ffffffff ffffffff ffffffff
f0: ffffffff ffffffff 01110f1a ffffffff
Capabilities:
50: CapID 01 PwrMgmt Capability
51: NextPtr 60
52: PwrMgmtCap c842 PMED0 PMED3Hot PMED3Cold Version=2
54: PwrMgmtCtrl 0000 DataScale:0 DataSel:0 D0
60: CapID 05 MSI Capability
61: NextPtr 00
62: MsgCtrl 64BitCapable MultipleMsgEnable:0 (0x1) MultipleMsgCapable:0 (0x1)
64: MsgAddr 0
68: MsgAddrHi 0
6c: MsData 0
PCI Configuration Space (Segment:0000 Bus:00 Device:1c Function:00)
Common Header:
00: VendorID 8086 Intel Corporation
02: DeviceID 0f48
04: Command 0004 BusInitiate
06: Status 0010 CapList
08: RevisionID 11
09: ProgIF 00
0a: SubClass 04 PCI-PCI Bridge
0b: BaseClass 06 Bridge Device
0c: CacheLineSize 0010 BurstDisabled
0d: LatencyTimer 00
0e: HeaderType 81
0f: BIST 00
10: BAR0 00000000
14: BAR1 00000000
18: PriBusNum 00
19: SecBusNum 01
1a: SubBusNum 01
1b: SecLatencyTmr 00
1c: IOBase f0
1d: IOLimit 00
1e: SecStatus 2000 InitiatorAbort
20: MemBase fff0
22: MemLimit 0000
24: PrefMemBase fff1
26: PrefMemLimit 0001
28: PrefBaseHi 00000000
2c: PrefLimitHi 00000000
30: IOBaseHi 0000
32: IOLimitHi 0000
34: CapPtr 40
38: ROMBAR 00000000
3c: IntLine 10
3d: IntPin 01
3e: BridgeCtrl 0000
Device Private:
40: 01428010 00008000 00100000 01313c12
50: 10010040 0004b260 00000000 00000000
60: 00000000 00000016 00000000 00000000
70: 00010002 00000000 00000000 00000000
80: 00009005 00000000 00000000 00000000
90: 0000a00d 0f488086 00000000 00000000
a0: c8030001 00000000 00000000 00000000
b0: 00000000 00000000 00000000 00000000
c0: 00000000 00000000 00000000 00000000
d0: 0000c000 00000842 c9118000 00000000
e0: 00000000 00000000 00000004 00000000
f0: 00000050 000000c0 01110f1a 01000000
Capabilities:
40: CapID 10 PCI Express Capability
41: NextPtr 80
42: Express Caps 0142 (ver. 2) Type:Root port
44: Device Caps 00008000
48: Device Control 0000 MRR:128 ns ap pf et MP:128 ro ur fe nf ce
4a: Device Status 0010 tp AP ur fe nf ce
4c: Link Caps 01313c12
50: Link Control 0040 es CC rl ld RCB:64 ASPM:None
52: Link Status 1001 SCC lt lte NLW:x0 LS:2.5
64: DeviceCaps2 00000016 CTR:6 CTDIS arifwd aor aoc32 aoc64 cas128 noro ltr TPH:0 OBFF:0 extfmt eetlp EETLPMax:0
68: DeviceControl2 0000 CTVal:0 ctdis arifwd aor aoeb idoreq idocom ltr OBFF:0 eetlp
54: Slot Caps 0004b260
58: Slot Control 0000 pcc PI:?? AI:?? hpi cc pde mrls pfd ab
5a: Slot Status 0000 pds hpi cc pdc ms pfd ab
5c: Root Control 0000 pmei fs nfs cs
5e: Reserved 0000
60: Root Status 00000000 pmep pmes ID:0
80: CapID 05 MSI Capability
81: NextPtr 90
82: MsgCtrl MultipleMsgEnable:0 (0x1) MultipleMsgCapable:0 (0x1)
84: MsgAddr 0
88: MsData 0
90: CapID 0d Subsystem ID Capability
91: NextPtr a0
94: SubVendorID 8086
96: SubSystemID 0f48
a0: CapID 01 PwrMgmt Capability
a1: NextPtr 00
a2: PwrMgmtCap c803 PMED0 PMED3Hot PMED3Cold Version=3
a4: PwrMgmtCtrl 0000 DataScale:0 DataSel:0 D0
1e
PCI Configuration Space (Segment:0000 Bus:00 Device:1f Function:00)
Common Header:
00: VendorID 8086 Intel Corporation
02: DeviceID 0f1c
04: Command 0007 IOSpaceEn MemSpaceEn BusInitiate
06: Status 0210 CapList DEVSELTiming:1
08: RevisionID 11
09: ProgIF 00
0a: SubClass 01 ISA Bridge
0b: BaseClass 06 Bridge Device
0c: CacheLineSize 0000
0d: LatencyTimer 00
0e: HeaderType 80
0f: BIST 00
10: BAR0 00000000
14: BAR1 00000000
18: BAR2 00000000
1c: BAR3 00000000
20: BAR4 00000000
24: BAR5 00000000
28: CBCISPtr 00000000
2c: SubSysVenID 8086
2e: SubSysID 0f1c
30: ROMBAR 00000000
34: CapPtr e0
3c: IntLine 00
3d: IntPin 00
3e: MinGnt 00
3f: MaxLat 00
Device Private:
40: 00000403 fed03002 00000503 fed0c002
50: fed08002 fed01002 fef00002 fed05002
60: 00000000 00000000 00000000 00000000
70: 00000000 00000000 00000000 00000000
80: 00000001 00000000 00000000 00000000
90: 00000000 00000000 00000000 00000000
a0: 00000000 00000000 00000000 00000000
b0: 00000000 00000000 00000000 00000000
c0: 00000000 00000000 00000000 00000000
d0: 00000000 00000000 0000ffcf 00000000
e0: 100c0009 00000000 00000000 00000000
f0: fed1c001 00000000 01110f1a 00000303
Capabilities:
e0: CapID 09 Vendor Specific Capability
e1: NextPtr 00 -
I want to write data into eeprom(93LC86) in parallel port using labview?
I want to write data into eeprom(93LC86) in parallel port using labview? Also I want to read data from EEprom.
Hi Mr. Mz,
after having a look to 93LC86-Datasheet I do not see a problem. The self-timing programming cycle of this Chip avoids timing problems; the rest is only logical stuff.
If you need more general info, how to use the parallel port, I recommend: http://[email protected]/ or
in case you need an example of SPI-Interface in LabVIEW with paraport - then write to: [email protected]
You are welcome
regards
wha -
Trigger and compare waveforms then write to file
I am trying to make a coincidence between two channels without using a SCA. I have a Tek DPO 7104 scope where I have two PMT's connected. PMT1 is on channel 1 and PMT2 is connected to channel 2. I have my current vi setup to trigger on channel 1. I generate a waveform that has both channels in the waveform data. My goal is to make a comparsion between channel 1 and channel 2. If channel 2 is "similiar" to channel 1, then write to file. If the two channels are not similiar then do not write and go back and wait for another trigger. I am thinking of using the "index array" to extract each channel seperately. The next part would be to make a comparison somehow. I was hoping someone might have an example that would help me to accomplish this. I have been reading the post but I have not found an example that will assist me. I would really appreaciate some help.
ChadJust in case someone stumbles across this in the future, this discussion moved here:
http://forums.ni.com/t5/LabVIEW/waveform-comparison/td-p/1158717
Justin Parker
National Instruments
Product Support Engineer -
I've looked, but I cannot find a writer that lets you write to a specific line of a file. Like:
blabla.write("text",lineNumber);Is there such a writer?ok :-)
import java.util.*;
import java.io.*;
- read the file using a buffered reader.
File yourFile = new File("...");
byte[] buf = new byte[file.length()];
try {
FileInputStream fis = new FileInputStream(yourFile);
fis.read(buf,0,file.length());
fis.close();
} catch(IOException e) { e.printStackTrace(); }
- localize the CRs (carriage return, symbol that indicates a line change) (you can do that very easily (but not very efficiently) with a StringTokenizer.
String str = new String(buf, "US-ASCII"); // or whatever charset
StringTokenizer stk = new StringTokenizer(str, "\r\n", false);
- Load a java.util.Vector with every "line" (each line now becomes a element in the Vector).
Vector lines = new Vector();
while (stk.hasMoreTokens()) {
lines.add(stk.nextToken());
- You can now add and remove lines by using insert and remove from the Vector.
System.out.println(lines.get(10)); // prints line 10
lines.add("Hi how are you"); // appends a line
lines.insert(10, "Hi how are you"); // adds this line at line 10
- When it is time to save, iterate thru the Vector and concatenate every elements of the Vector into a StringBuffer.
StringBuffer strb = new StringBuffer("");
for (Enumeration e = lines.elements() ; e.hasMoreElements() ;) {
strb.append(e.nextElement());
- Finally overwrite the original file with the new data.
try {
FileOutputStream fos = new FileOutputStream (yourFile, false);
fos.write(strb.toString("US-ASCII")); // or whatever
fos.close();
} catch(IOException e) { e.printStackTrace(); }
Tell me if it's better.
Anthony -
[SOLVED] After post trigger go to the specific item. (Oracle Forms 10g)
I have this layout
http://img339.imageshack.us/img339/975/capturetbo.png
and a post trigger insert and update
IF :item1 IS NULL
AND :item3 IS NOT NULL THEN
alert_id := FIND_ALERT('blank_alert');
SET_ALERT_PROPERTY(alert_id,ALERT_MESSAGE_TEXT,'Item3 must have a value.');
v_alert := SHOW_ALERT(alert_id);
RAISE Form_trigger_Failure;
END IF;My problem was as it fires, the cursor will be on the item1.
I've already use
SET_ITEM_INSTANCE_PROPERTY
NEXT_ITEM
GO_ITEMbut it was all illegal. The cursor must be in the item3.
Don't question me why I do not set the item3 to required and why post triggers.
It is just that. It is the requirement.
Any bright Idea? Thanks!
And even when-validate-item triggers. It must be post triggers.
Is it possible? Thanks.
Edited by: reppihsrow on Feb 19, 2013 6:02 PMPOST-TRIGGER
DECLARE
timer_id TIMER;
one_second NUMBER := 1000;
BEGIN
<validations . . .>
timer_id := CREATE_TIMER('timer', one_second,NO_REPEAT);
END;WHEN-TIMER-EXPIRED
GO-ITEMBright idea! Million thanks!
Note: I have an typo error in my code. It should be
IF :item3 IS NULL
AND :item1 IS NOT NULL THENAgain. Thanks! -
Write to i2c Register from java
My setup: Java 1.5, SUSE Linux 10.2
I'm trying to set registers over i2c.
From command line this can be done using "i2cset [options] [bus_address] [chip_address] [register] [value] b".
I'd like to do this without using the command line, directly from java (may be using JNI and some native libraries).
I searched google, tried to find some examples at koders.com - but no luck.
I hope someone can point me in the right direction... Any hint on this subject is highly appreciated!Yes, as I described, i don't want to use Runtime.exec().
There are many registers which have to be set alternating, so i2cset has to be executed over 4 times a second - which is bad.
I'm currently doing this in my application:
ProcessBuilder pb = new ProcessBuilder(new String[] { I2C_SET_CMD, I2C_OPTION_NOQUESTIONS, I2C_BUS_ADRESS,
I2C_CHIP_ADRESS, register, value, "b" });
Process p = pb.start();
int exitCode = p.waitFor();The problem is, that there are Filehandles left open (by i2cset?? I think so...) and that crashes linux after some hours of operating (to many open files).
That's the reason, why I'm looking for a solution without Runtime.exec() and especially without using ic2set.
At the moment I don't have native libraries or even native code to do this. Is there a native library which can be used from within java to set i2c Registers?
Or is it somehow possible to do address i2c registers directly from java (whitout using native code)? -
Write/read to eeprom via RS232
Hallo the community,
I want to write an application with Labview which can read or write an EEPROM. i'm using an ATMEGA 128L von ATMEL. Do some one knows wether dies works in labview. If then where can I find programmsample approching the solution that i m searching.
Thank you for any help.
Alain K.I have written LV programs to talk to PROM programmers. You need to know two basic things: The communications protocol to the programming device and the data format that the programming device can accept. Once you have this information, it should be possible to write the program in LV. I did a quick search on the ATMEGA 128L. It appears to have an RS-232 interface so the communications from LV should not be a problem. The data interface may require some bit manipulation, but LV can be quite versatile in that regard.
There may be some tedious work involved, but I think it is feasible to do what you want.
Lynn -
Can someone help me create a vi to read and write to an EEPROM using HSDIO?
I'm trying to create an EEPROM scanner/programmer using a PXI-6541. I have some EEPROMs with 24 address lines and 16 data lines. I want to scan addresses 0000h to 8000h and log the data in a file so I can program other EEPROMs with the same data. Can someone help me get started with this, please?
Hey jallen_100,
It sounds like you are trying to do something similar to this Memory Test Reference Design. Check out the code linked at the bottom of the document, and try using part of the code that fits your need, and modify the rest that you don't need, or that won't work with your device. Also, are you going to be using more than the 32 channels of the one board, or will you require 2 devices? If so, then you should check out the Tclk examples, but if not then the above should be enough to get you started. Hope this helps get you started, or at least an idea of what you might be able to do.
Regards,
DJ L. -
Best way to chain several I2C write / read cycles
Hi,
I'm developing a custom sensor that communicates over I2C with the NXT.
I need to perform sequencially several read / write actions over I2C.
I know that the NXT toolkit is limited to only one frame sequences and that is possible to chain them with "pink NXT wires" or "any other wire".
I've tried several times but I only get the first frame working. The other aren't executed.
Does anyone here has enough experience or advices to perform several I2C operations sequencially in the same VI.
Many thanks in advance.What version of LabVIEW / NXT Module are you using?
The most recent LVLM supports multi-frame stacked sequences.
Take a look at the ultrasonic sensor block diagram, it has a configure step followed by actually reading the data.
One problem can be trying to read/write the i2c channel too fast. You may need to insert some arbitrary wait times in between sequential i2c calls.
If you post your code it might be easier to tell whats not working. -
Enable exception handling in trigger
Hello-
I am fairly new to Oracle, and have written a simple audit trigger to insert old values into an audit table upon updates to an existing table. I am trying to incorporate some exception handling in case there are errors. Is there a way to 'enable' or call out the oracle predefined the errors, or do I have to specifically write conditions for all the exceptions I want to capture?
Thanks!Hi
There are two types of expections exists in oracle, i.e. internal & external exceptions. Internals are oracle defined and externals are user defined.
Internal
When no_data_found
when too_many_rows
when divide_zero (read oracle documentation for more)
example:
declare
begin
select ename,sal from emp where empno=0;
exception
when no_data_found then
dbms_output.put_line('No such employee exists');
end;
external
=======
you define in the declaretive part
example:
declare
MyException exception
begin
if .... then
raise MyException;
end if;
exception
when Myexception then
do_action
end; -
Hello,
I have problems with my trigger. I want to know in witch polygon a point is. When I create a select-statement like this
select p.fid, p.FID_SG_OBJEKT_O, f.fid from POINT p, POLYGON f where SDO_INSIDE (p.GEOM, f.GEOM) = 'TRUE'
then I have no problems. It works fine.
Now a trigger should do this work:
create trigger ...
begin
select fid into :new.FID_SG_OBJEKT_O from POLYGON where SDO_INSIDE (:new.GEOM, GEOM) = 'TRUE';
end;
Then following message I get:
execution error, ORA-13226:
I rebuild all spatial-triggers without errors.
Do you know what's wrong?
Thanks!
Edited by: user3163638 on 24.10.2008 00:01the first geometry inside the sdo_INSIDE must come from a table and have a spatial index (that is also what your ora error is a saying).
http://download.oracle.com/docs/html/B14255_01/sdo_operat.htm#sthref1036:
geometry1 Specifies a geometry column in a table. The column must be spatially indexed. Data type is SDO_GEOMETRY.
actually you want to know what is the polygon that contains the input point.
http://download.oracle.com/docs/html/B14255_01/sdo_operat.htm#sthref1036
if the point table has the trigger on it you should write it as:
select fid into :new.FID_SG_OBJEKT_O from POLYGON p where SDO_CONTAINS (p.GEOM, :new.geom) = 'TRUE';
Not sure how you defined :new (and maybe :old) could be that the parameter inside the sdo_contains should :old.geom.
Hoping this helps you out.
(additionally check your requirements to cover the case where a point is on the boundary of 1 or multiple polygons)
Luc
Edited by: lucvanlinden on Oct 24, 2008 10:22 AM -
How can I write to multiple daisy-chained network serial addresses through a single COM port?
I have a VI to write to 3 PI Mercury motor controllers using daisy chained RS232 connected via a Prolific USB-to-Serial adapter. I know that it is possible to talk to the individual controllers because the PI terminal that I have recognises the addresses of multiple controllers and designates them Device 1,2,3. The VISA resource name when configuring the port just comes up as COM5 most of time, with seemingly no way to specify an address on that COM port. Occasionally the VISA resource is ASRL5::INSTR and as this is disconnected and re-connected, this address moves up a number (e.g ASRL7::INSTR). Can anybody tell me how I can configure my serial communication to allow me to individually communicate with the different devices through a single COM port?
What does the manual say about addressing? RS-232 is not multidrop, the resource name is correct, and there is no additional configuration needed. There would have be a specific write in order to address a certain controller.
-
How to retreive dynamicly the name of a trigger associated with a table
Hi,
Comming from Ms-Access and SQL Server, i use triggers (build by omwb) to get automaticaly a new value to primary keyes (during the insert phase).
Is it possible to retreive by sql, schema... the name of a trigger associate to a specific col in a specific table ?
Regards.Hi,
Comming from Ms-Access and SQL Server, i use triggers (build by omwb) to get automaticaly a new value to primary keyes (during the insert phase).
Is it possible to retreive by sql, schema... the name of a trigger associate to a specific col in a specific table ?
Regards. For update triggers try this:
select trigger_name from all_trigger_cols
where
table_owner = 'DEMO' and
table_name = 'DEMO_BILLING' and
column_name = 'PAID' and
column_list = 'YES';
For insert triggers you can refer to all_triggers.
Regards,
Robin.
Robin Bothwell
Software Developer
Compuware/Numega
1-800-462-7740x16609
<http://www.compuware.com/products/devpartner/db/visualstudio.htm>
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