Vivado 2015.2 Integrate Zynq PCIe Design and adder - IP Integrator

Hi Friends,
I am new to Xilinx vivado i want to integrate 7series pcie to adder_sub ip.
I dont know how to integrate it please provide me solution how to integrate it
I have basic example to of integrating axi example in the vivado tool.
but same thing i am trying for pcie and its not working
I am using ZC706 board.
Thanks for the support

Hello ,
Check if any of the following Links are useful:
http://www.xilinx.com/training/vivado/designing-with-vivado-ip-integrator.htm
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug995-vivado-ip-subsystems-tutorial.pdf
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug994-vivado-ip-subsystems.pdf
http://www.xilinx.com/support/documentation/university/Vivado-Teaching/Digital-Design/2014x/docs-pdf/Vivado_tutorial.pdf
--Syed

Similar Messages

Porting Xapp1198 to Vivado 2015.2

Hi,
I'm trying to port Xapp1198 (transceiver eye scan reference design) to Vivado 2015.2 for Zynq ZC706 board.
The original reference design was compiled with Vivado 2014.4.
After sucessfully upgrading IP I run Block Design validation of the eyescan_subsystem, and getting a bunch of errors shown in the attached screenshot.
I'd appreciate if this reference design is released for the latest Vivado 2015.2.
Thanks,
Evgeni

Hi Muzaffer,
I'm trying to fix this error message given by Vivado during the implementation phase (place & route): [Opt 31-30] Blackbox FIfoA (sfifo_16x8_dr) is driving pin DI[1] of primitive cell sv_op_R1_reg[3]_i_1. This blackbox cannot be found in the existing
I used entity instantiation of this fifo in my RTL (fifo_i0 : entity target_lib.sfifo_16x8_dr). If Vivado is giving me this error, I'm assuming that it is expecting the Fifo to be in the target_lib library. That why I want to be able to change the library. So, if Vivado ignores library constructs during implementation, how comes I am getting this error?

FreeRTOS_drc : invalid command name "xget_libgen_proc_handle" problem - Vivado 2015

Hi,
We are using Vivado 2015.2 for Zynq. While creating a new app and a bsp with FreeRTOS in sdk, we received the following error:
ERROR : [ Hsi 55-1545 ] Problem running tcl command ::sw_freertos_zynq_v1_02_a::FreeRTOS_drc : invalid command name "xget_libgen_proc_handle" while executing
"xget_libgen_proc_handle" (procedure "::sw_freertos_zynq_v1_02_a::FreeRTOS_drc" line 5) invoked from within
"::sw_freertos_zynq_v1_02_a::FreeRTOS_drc freertos_zynq"
[ Hsi 55-1440 ] Error(s) while running DRCs.
ERROR : Error generating bsp sources : Failed to generate BSP.
While we were using in ISE 2014.7, there wasn't any problem. However, we have to use Vivado 2015, because it is necessary for co-simulation for zynq.
Could you help? Thanks.

Follow the readme file from the latest information download. The standalone bsp found in the latest info download for 2014.4 includes a newer bsp (version 4.2).

VIVADO 2015.2, DisplayPort AXI frequency cannot be changed

Hi All,
It looks like a simple problem, but changing the AXI Lite clock frequency is impossible (DisplayPort 6.0, VIVADO 2015.2). See below.
set_property -dict [list CONFIG.AXI_Frequency {100}] [get_bd_cells inst_displayport]
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'AXI_Frequency' from '50' to '100' has been ignored for IP '/inst_displayport'
Is this a simple bug? Should I ignore it?
Also, what is this new setting called "SS mode"? It's not explained in the pg064.
Thank you
Vlad

Hi
Do you have all the IPs updated ?
Go to Tools --> report --> report ip status and check if all the IP's are up to date. In case they are not up to date, upgrade them.
If all IP's are up to date try regenerating block design output products (reset output products followed by generate output products).
Also, you need to add the User IP to Vivado IP repository.
You can refer to page-68 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug896-vivado-ip.pdf to know how to add user IP to IP repository.

ISE 14.4 BitGen Failing After Vivado 2015.1 Installation

My node-locked version of Embedded Edition ISE 14.4 has started failing Bitgen with the following warning:
WARNING:Bitgen:26 - Bitgen only supports DRC but not bitstream generation on
   this device. This condition can occur if there are problems obtaining a
   license to run bitgen or if the design targets a device which is Early
   Access.
I have not changed my ISE license file recently, but I have installed Vivado 2015.1 in the last couple of days. Sythesis and Implementation still work. The License Configuration Manager that I can open from the Help menu still indicates that I have permanent licenses for all the features (i.e., nothing has changed to the best of my knowledge).
Could the Vivado install have messed up my ISE licensing? If so, how do I fix this problem?

Hi ,
Are there more than one ISE licenses in the installation directory?
Please attach the Xinfo file so that we can check if the correct license is being accessed by ISE.
(also post the name of those .lic files)
To generate the xinfo file:
Start --> All Programs --> Xilinx Design Tools --> ISE Design Suite 14.x --> Accessories --> Xinfo System Checker.
Thanks,
Tushar.
Please mark the post as an answer ("Accept as solution") in case it helped resolve your query.
Give kudos in case a post guided you to the solution.
This will help others in the long run

Vivado 2015.2 IP Packager Fail

Vivado 2015.1 IP packager works fine. In 2015.2 the tool seems to indentifty all the parts of my design correctly and displays well in the Hierarchy window. But when I try to ipx::package_project in 2015.2 it fails with "ERROR: [IP_Flow 19-272] [HDL Parser] Unable to determine HDL language of top-level HDL model, /..."random.coe. It seems like the packager thinks the coe is the top-level design. Any idea how to fix?

Yes the top is selected properly. No I cannot post my design here.
If you want to reproduce the failure just try making any .sv your top level. And make sure the project includes a .coe. The packager will fail. Then use a .v as a top level and it will work. There's a bug in the tool.
A workaround is to make your top (System Verilog) use the extension .v Then explicitly label the file system verilog with "set_property type systemVerilogSource" in Vivado. Now it will package properly.
Please fix in a patch or 2015.3.
Thanks
jer

Vivado 2015.1 PS7-GMII EMIO broken. Solution inside!

Hi,
I have found a huge bug in Vivado 2015.1 when using PS7 GMII on EMIO in a BD design.
It is impossible to use the PS7 ENET with routing the GMII through EMIO. The problem is thet ENET0_GMII_TXD ENET0_GMII_TXEN and ENET0_GMII_TXER is permanently set to Ground.
Solution:
The following file defines the ps7 wrapper when the ps7 instance is created in the BD
$(XILINX_INSTALL_DIR)Vivado/2015.1/data/ip/xilinx/processing_system7_v5_5/ttcl/processing_system7.ttcl
In this file the ENET GMII TX signals are *REMOVED*!!! (They are commented out.)
So I activated the signals and ethernet is working again.
I have create a patch (see below) which shows the problem.
So Xilinx, is any reasonable explanation out there for this? I guess a lot of mainboards requiere an EMIO Ethernet configuration.
--- processing_system7.ttcl 2015-05-20 13:42:34.978734005 +0200
+++ processing_system7.ttcl.org 2015-04-22 07:30:05.000000000 +0200
@@ -1070,8 +1070,8 @@
wire [11:0] M_AXI_GP1_RID_FULL;
-wire ENET0_GMII_TX_EN_i;
-wire ENET0_GMII_TX_ER_i;
+//wire ENET0_GMII_TX_EN_i;
+//wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
@@ -1655,8 +1655,8 @@
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
- ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i;
- ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i;
+ ENET0_GMII_TX_EN <= 1'b0; //ENET0_GMII_TX_EN_i;
+ ENET0_GMII_TX_ER <= 1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
@@ -3134,9 +3134,9 @@
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
- .EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
- .EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
- .EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
+ .EMIOENET0GMIITXD (), // (ENET0_GMII_TXD_i ),
+ .EMIOENET0GMIITXEN (), // (ENET0_GMII_TX_EN_i),
+ .EMIOENET0GMIITXER (), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),

Does not work for me.
I re-run my 15.1 project in 15.2 and silll getting ENET1_TX pins tied to GND.
Tried to re-generate block design, unset/set ENET1 - no effect.
Tried to apply patch for 15.1 (added directory in D:\Xilinx\Vivado\2015.1\patches\AR64531_Vivado_2015_1_preliminary_rev1) then run in 15.1 - no effect
I noticed that in processing_system7_v5_5_processing_system7 parameter C_EN_EMIO_ENET1 = 0, which blocks TX ports connection.
Help needed.

Clocking Wizard broken in Vivado 2015.2?

Because I'm lazy and I didn't want to compute the PLL/MMCM parameters by hand (some kind of online calculator would be a great tool IMHO), I started up the GUI mode of Vivado 2015.2 and wanted to use the Clocking Wizard IP (which I remebered would do the calculations). To my surprise, this rather basic IP doesn't work anymore.
When trying to add this IP, I get a pop-up with the following error message:
Error occurred while initializing 'clk_wiz_0'
Tcl error in update procedure while setting value 'MMCM' on the parameter 'PRIMITIVE'.
unexpected "," outside function argument list
in expression "1000 / 10,000"
The TCL console has some more Details on the issue:
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 clk_wiz_0
unexpected "," outside function argument list
in expression "1000 / 10,000"
ERROR: [IP_Flow 19-3188] Error occurred while initializing 'design_1_clk_wiz_0_0'
Tcl error in update procedure while setting value 'MMCM' on the parameter 'PRIMITIVE'. unexpected "," outside function argument list
in expression "1000 / 10,000"
CRITICAL WARNING: [IP_Flow 19-973] Failed to create IP instance 'design_1_clk_wiz_0_0'. Error during customization.
ERROR: [#UNDEF] Error occurred while initializing 'design_1_clk_wiz_0_0'
Tcl error in update procedure while setting value 'MMCM' on the parameter 'PRIMITIVE'. unexpected "," outside function argument list
in expression "1000 / 10,000"
ERROR: [BD 5-7] Error: running create_bd_cell.
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
How to reproduce:
start Vivado in GUI mode
create a New Project (select RTL, no sources, Zedboard)
select Clocking Wizard from the IP Catalog
Is there a problem with my installation (it should be clean/new) or is that a problem with the IP/config?
Thanks in advance,
Herbert

problem with system language settings, Check this to workaround
http://forums.xilinx.com/t5/Design-Entry/clocking-wizzard-throws-error-while-instantiating-in-IPI/td-p/584056
http://forums.xilinx.com/t5/Design-Entry/Connection-Automation-failed-with-a-simple-MicroBlaze-design/td-p/539137

Vivado 2015.1 unattended installation - Can someone help pls

i tried installing Vivado 2015.1 in batch mode
After running app at command prompt %~dp0"xsetup2.bat" -b ConfigGen it came up with 4 options to choose from, i selected option 2 Vivado Design Edition then the dialog box Disappeared without prompting for a location/filename for
configuration file to be stored.
Can someone help pls.

Thanks Vinay...
Have checked the root of C and the App folder but i can't find any changes..
below is the command in the batch file.... could this make any diff please?
@echo off
REM store the original image dir into a variable
set INSTALLER_ROOT_DIR=%~dp0\..
rem resolve UNC path
pushd %~dp0
set root="%cd%"
rem xsetup.bat is in <root>\bin, get the parent directory (<root>)
set parent=%cd%\..
@setlocal enableextensions enabledelayedexpansion
rem Check for exclamation point
rem Remove exclamation point if any in the parent folder path and check if the folder exists
set parent_fixed=%parent:!=%
IF NOT EXIST "%parent_fixed%" (
start cmd /c "echo ERROR: The character '^!' is not allowed in path. Please correct the problem and try again. && pause"
endlocal
goto :end
endlocal
CALL %root%\setup-boot-loader.bat %*
set ARGS=%ARGS% -DINSTALLER_ROOT_DIR="%INSTALLER_ROOT_DIR%"
REM if the argument -Uninstall was specified, run the uninstaller
IF NOT [%1]==[] (
IF [%1]==[-Uninstall] (
set ARGS=%ARGS% -DINSTALLATION_MODE=Uninstall
set ARGS=%ARGS% -Dlog4j.configuration="%parent%/data/log4j.xml"
IF NOT "%DEBUG_ARGS%" == "" (
echo adding %DEBUG_ARGS% to %ARGS%
set ARGS=%DEBUG_ARGS% %ARGS%
set ARGS=%ARGS% -DHAS_DYNAMIC_LANGUAGE_BUNDLE=true
IF [%X_BATCH%] == [1] (
rem Check if it is a 32-bit platform and exit if 32 libraries are not available.
IF [%ARCH%] == 32 (
set libDir=%parent%\lib\win32.o
IF NOT EXIST "%libDir%" (
echo ERROR: This installation is not supported for 32 bit platforms
goto :end
%X_JAVA_HOME%\bin\java.exe %ARGS% -cp "%X_CLASS_PATH%;%parent%\lib\classes\commons-cli-1.2.jar" com.xilinx.installer.api.InstallerLauncher %*
) ELSE (
%X_JAVA_HOME%\bin\java.exe %ARGS% -splash:"%parent%\data\images\splash.png" -jar "%parent%\lib\classes\xinstaller.jar"
goto :checkCanceled
goto :end
:checkCanceled
IF EXIST %TEMP%\xinstall-delete.bat (
call %TEMP%\xinstall-delete.bat
del %TEMP%\xinstall-delete.bat
:end
IF NOT [%TEMP_NATIVE_LIB%] == [] (
IF EXIST [%TEMP_NATIVE_LIB%] (
RMDIR /Q /S [%TEMP_NATIVE_LIB%]
popd

Looking for DPS designer and developper freelancer

Hi everybody
i've got a very interesting project to deliver
I am looking for freelancers who have a very good experience working on DPS and Idesign, here is the brief, if you think you can help and want to make good money please shout: [email protected]
BRIEF
objective:
create a digital version of 3 print magazines about home design and crafting : Ipad / android tablets and flash desktop
tool:
Adobe digital publishing suite, Indesign extension (software already used by the company) to :
- Recontextualize / files the Indesign files my companie ueses to create folios / templates adapted/intended for the digital version of the magazines.
- To sell digital magazines directly on the app store, marketplace, and others.
Mission:
- Create a whole range of folios / template that fits the style and the reading experience of each magazine.
- Integrate the icons, multimedia and other elements created specifically for the digital version
- Take the items Indesign files that have been done for the paper magazine version for the first quarter 2013 and lay them out entirely in the digital version.
- assist on how to use DPS from folios creation to sales with a person specially recruited within my company and enable him to build digital versions every quarter without too much assistance.

We are based in NYC and we would need somebody to work out of our offices.

Sharing an external sample clock between PCI-6722 and PCI-6602

I need PCI-6602 work with PCI-6722。6602 shares 6722’s ao/SampleClock as external clock and triggered by 6722’s ao/StartTrigger。The master device is 6722, which refered as Dev1, and the slave device is 6602, which refered as Dev2. A RTSI line is used to connect the two devices correctly.
I use C API to finish my program and my code is as follows:
//config 6722 analog out task
1、DAQmxCreateTask("NI6672", &hAOTask);
2、DAQmxCreateAOVoltageChan(hAOTask, "Dev1/ao0", "", -10.0, 10.0, DAQmx_Val_Volts, "" );
3、DAQmxCfgSampClkTiming(hAOTask, "", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
4、DAQmxWriteAnalogF64(hAOTask, 1000, 0, 10.0, DAQmx_Val_GroupByChannel, data, NULL, NULL);
//config 6602 counter task
5、DAQmxCreateTask("NI6602", &hCounterTask);
6、DAQmxCreateCICountEdgesChan(hCounterTask, "Dev2/ctr0", "", DAQmx_Val_Rising, 0, DAQmx_Val_CountUp);
//use /Dev1/ao/SampleClock for external clock
7、DAQmxCfgSampClkTiming(hCounterTask, "/Dev1/ao/SampleClock", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
//use /Dev1/ao/StartTrigger
8、DAQmxSetTrigAttribute (hCounterTask, DAQmx_ArmStartTrig_Type, DAQmx_Val_DigEdge);
9、DAQmxSetTrigAttribute (hCounterTask, DAQmx_DigEdge_ArmStartTrig_Src, "/Dev1/ao/StartTrigger");
10、DAQmxSetTrigAttribute (hCounterTask, DAQmx_DigEdge_ArmStartTrig_Edge, DAQmx_Val_Rising);
//start counter task first
11、DAQmxStartTask(hCounterTask);
//start 6722 task
12、DAQmxStartTask(hAOTask);
I run it on the MAX virtual Device, and the Step 11always returned -89120。
I try to slove this problem, so I change the Step 7, use /Dev2/PFI9 to instead of /Dev1/ao/SampleClock.
7、DAQmxCfgSampClkTiming(hCounterTask, "/Dev2/PFI9", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
The code runs well, but I don’t know which terminal is connected by /Dev2/PFI9. Does it connect to /Dev1/ao/SampleClock？
I use another API DAQmxConnectTerms to ensure that, I add a Step before Step 11.
DAQmxConnectTerms( "/Dev1/ao/SampleClock", "/Dev2/PFI9", DAQmx_Val_DoNotInvertPolarity );
The program also run well. But I am still not sure that 6602 is sharing /Dev1/ao/SampleClock。If not, which terminal of Dev1 is connected by /Dev2/PFI9?
Is my code right? If not, hwo to fix my code or supply some example for me? Thanks.

Hello Shokey,
From looking over your post, it looks like you want to program in C, using simulated instruments, a master/slave design with a PCI-6602 and PCI-6722. The PCI-6722 is the master device and the PCI-6602 is the slave device. In order to implement this with the real cards, you would need a RTSI cable between the 2 cards in order to pass the triggers and the sample clock. Unfortunately with simulated devices you can't implement this so parts of your code won't be able to work exactly like if you had the instrument.
If you did have the instrument, you can implement this by performing the following steps:
Master Device:
1.) Export the ao/SampleClock and ao/StartTrigger to a RTSI Line. (See DAQmx C Reference help for DAQmxExportSignal to export these)
Slave Device:
1.) Set the Sample clock and the trigger to the RTSI.
There is another forum that I think will help you out to implement this correctly. In this forum, the customer was trying to export a trigger through a RTSI and the problem he was experiencing was a broken RTSI cable. His code, he states, works. I hope this helps you with this and if you have any more questions, feel free to post.
Jim St
National Instruments
RF Product Support Engineer

Show information in log file under Vivado 2015.1?

In XST and in Vivado through 2014.4 I used something like:
assert false report "FFV_D sees KEEP_HIERARCHY: " & Value(KeepHierarchy) severity NOTE;
to figure out what was going on in Vivado during synthesis.
With Vivado 2015.1, instead of the report from the constant condition assert statement, I now get:
WARNING: [Synth 8-312] ignoring unsynthesizable construct: assertion statement [h:/Eng/MVhdl/Src/Base/MReg.vhd:1731]
Is there some other means to write report information into the Vivado log during synthesis?
I most use this so that I can verify the state of generics within entities, but I use the mechanism all the time for debugging synthesis.
Ian Lewis
www.mstarlabs.com

Hello Brian,
I certainly hope that Vivado has some means of reporting from within HDL.
I agree that removing static condition assert support is a horrible idea, especially since the Vivado synthesis log does not provide even as good information as XST did: http://forums.xilinx.com/t5/Synthesis/Requests-for-Vivado-synthesis-log-changes/td-p/590481 . Or, at least, I cannot interpret the Vivado synthesis log at all well.
I have not yet read enough copies of the log for different conditions to be sure that it is fundamentally unclear, but more and more it looks to me like it just does not include enough information for anyone to know exactly what Vivado has done with respect to generic bindings for specific instances. I know it does not include enough information to even have a clue what it has done with respect to applying attributes.
In any case, even if Vivado synthesis provided a perfect and complete implementation of VHDL, and its log contained every bit of information one could imagine wanting to show how it binds entities and generics, it is essential to be able to see what the compiler is really doing at the level of one's own code: you can read the LRM until you are blue, but at some point you need to see what is really happening in a specific instance of code.
And, there is good reason to report into the log some facts about how one configured an entity at a higher level than the individual generics so you can quickly see that you did what you intended to do.
I could live with changing our asserts to something else, but some means to report into the log is important. It is not just some whim.
Ian Lewis
www.mstarlabs.com

Can we integrate a report designed in CR2008 into VS2010?

Hello,
1. Can we integrate a report designed in CR2008 into VS2010 ?
2. Our client has obtained license only for CR2008 (bought a single case) and we too develop/design .rpt file in CR2008 , So is it enough to install only CR2008 run time in the client machine to launch the Report in VS2010 application (.Net 4.0) or do we need to install SAP Crystal Report for Visual Studio 2010 run time in client machine to launch the report?
Thanks & Regards,
Mani G.S.

Hi Mani,
1. No. CR 2008 is not compatible / tested/ supported with VS 2010.
Only CR for VS 2010 is supported and meant to work with VS 2010.
2. Please refer to my response in below thread.
[Few quesions about SAP Crystal Report for Visual Studio 2010 and CR2011|Few quesions about SAP Crystal Report for Visual Studio 2010 and CR2011]
Please do not post same the question in multiple threads.
- Bhushan.

When attempting to create an SSRS Report in SharePoint 2010 Dashboard Designer and change the Server Mode from Report Center to SharePoint Integrated

Hi,
When attempting to create an SSRS Report in SharePoint 2010 Dashboard Designer and change the Server Mode from Report Center to SharePoint Integrated, I get the following unhandled exception:
************** Exception Text **************
System.InvalidOperationException: There was an error generating the XML document. ---> System.InvalidOperationException: Instance validation error: '2' is not a valid value for Microsoft.PerformancePoint.Scorecards.SqlReportViewData.SqlReportViewDataServerMode.
   at Microsoft.Xml.Serialization.GeneratedAssembly.XmlSerializationWriterSqlReportViewData.Write1_SqlReportViewDataServerMode(SqlReportViewDataServerMode v)
   at Microsoft.Xml.Serialization.GeneratedAssembly.XmlSerializationWriterSqlReportViewData.Write3_SqlReportViewData(String n, String ns, SqlReportViewData o, Boolean isNullable, Boolean needType)
   at Microsoft.Xml.Serialization.GeneratedAssembly.XmlSerializationWriterSqlReportViewData.Write4_SqlReportViewData(Object o)
   --- End of inner exception stack trace ---

Hi,
According to your post, an error occurred when you integrate SQL Server Reporting Services with SharePoint.
1. Please check the steps as the link below:
http://technet.microsoft.com/en-us/library/ff724283(v=office.14).aspx
2. Try to clean the configuration cache on all of your SharePoint servers and re-tested.
http://blogs.msdn.com/b/josrod/archive/2007/12/12/clear-the-sharepoint-configuration-cache-for-timer-job-and-psconfig-errors.aspx
Best Regards
Dennis Guo
TechNet Community Support

Ask the Expert: Cisco's 802.11ac Solutions - Deployment, Design, and Interop

Ask your Questions on Cisco’s 802.11ac Solutions - Deployment, Design, and Interop with Cisco Experts: Richard Hamby and Shankar Ramanathan.
Monday, March 30th, 2015 to Friday, April 10th, 2015
Richard Hamby is a senior technical support engineer and Team Lead of the Cisco Technical Assistance Center in Richardson, Texas. He is an expert in Indoor and Outdoor wireless for the full line of Cisco Unified and Converged Access Wireless products, as well as TAC Engineering Engagement Engineer liaison to project engineering teams for new Cisco wireless products. Prior to his current role, Richard was a customer support engineer with the AAA Security TAC team supporting Cisco identity management solutions and been with Cisco since 2009.
Shankar Ramanathan is a Customer Support Engineer at the Cisco Technical Center. He is a Technical Content Engineer and Subject Matter Expert for Cisco Enterprise Unified and Converged Access wireless mobility solution including Wireless LAN Controller 2500/5500/WISM2/7500/8500, Converged access 5760/3650/3850 switches, Access Points Lightweight and Autonomous, VoWLAN (792x/9971) , Cisco Prime Infrastructure SNMP management, Cisco Mobility Services Engine(MSE/ CMX). Prior to joining Cisco in November 2011, he worked as a wireless network engineer at Elan Technologies, responsible for RF wireless network planning, simulation, propagation path analysis, and optimization of Wi-Fi 802.11 mesh and WiMax (802.16 d/e) networks for various system integration and automation projects. Shankar holds a master of science degree in electrical engineering specializing in communications and signal process from the State University of New York, Buffalo. Shankar has a CCIE in Wireless(#40548) and CCNA certified (number 410004168640IMZF) and has over six years of industry experience.
Find other https://supportforums.cisco.com/expert-corner/events.
**Ratings Encourage Participation! **
Please be sure to rate the Answers to Questions

A common question we are asked is 'why is my device not achieving 11ac data rates?'
One of the most common answers relates to client compatibility/capability. To get the highest possible data rates of 11ac (assuming proper distance and RF health), the AP and the client device must both be capable supporting the requirements - 5GHZ, 80MHz Channel, short guard interval, 3 spatial streams. Each spatial stream has a max of 433.3Mb/s (at 80MHz, short GI).
The majority of 11ac-capable wireless cards on the market do not support 3 spatial streams. Most adapters in wireless-capable devices are 1SS or 2SS. For example, the Intel 7260 11ac adapter used in many devices is a 2SS adapter - therefore it's max possible data rate is 866.7. Another common adapter in use is the 11ac Broadcom 3SS that Apple uses in the newer Macbooks. These devices can achieve the 1.3GBs PHY data rate.
This guidance is the same for 11n adapters as well. To achieve max rate, your 11n AP and adapter must both support 40MHz channels, 3SS, short GI.
Note: The 11n and 11ac standards both define support for 4SS. 4SS-capable devices are rare, so 3SS is essentially our reality.
One of the most useful references for questions related to this topic is the AP Data Sheet for each AP. Here's the AP3700 for example:
http://www.cisco.com/c/en/us/products/collateral/wireless/3700-series-access-point/data_sheet_c78-729421.html
Table 1 lists the expected data rate per MCS Index value by #SS at each channel width and GI. Indexes 0-7 are the same for 11n and 11ac (11n limited to 40MHz channels of course). And MCS 8 & 9 are 11ac-only 256-QAM modulations.

Vivado 2015.2 Integrate Zynq PCIe Design and adder - IP Integrator

Similar Messages

Maybe you are looking for