Want to trigger event count from both counters (E) to buffer using FOUT (100kHz/16 or slower) as a trigger

We are using a AT-MIO-16E-1 board. We would like to run an xy raster pattern from the buffer (AO) in order to reduce scan times (256 x 256 pt images). At each AO (voltage) point we would like to read from both onboard counters and store the number of events counted to memory, reading out the buffer say every 256 pts (1 scan line). In order to ensure accurate counting periods the counters need to be triggered to coincide with some "dwell time" at each AO voltage pt. We have thought of using FOUT for the trigger or perhaps out analog out scanning signal but are concerned that the FOUT freq is too high (6250 khz - we would like 100hz-10khz). Any suggestions or e
xamples would be appreciated.

Hello;
The main problem there is going to be the counter triggering. I'm saying that because, there isn't a way for the Analog Input operation to send pulses that will trigger of the timer operation at multiple voltage levels. The only solution for this I can think of is, instead of having an analog voltage level which would indicate the position of xy, if you could have a device which would give a TTL pulse instead when the desired position is reached, then you could use the 6601 to have a triggered operation at the counter. Another constraint for your application right now is the fact that the E-series boards' counters don't have triggering features, only gated features.
Anyway, you would need to have a TTL pulse either to trigger (in case of the 6601 count
ers) or to gate (in case of the E-series board), when the desired XY position is reached.
Meanwhile, you can refer to the Labview examples for Streaming to disk, Analog I/O and counter operations. You can go to Search Examples->I/O Interfaces->Data Acquisition->Data Logger ( for streaming to disk operations); Search Examples->I/O Interfaces->Data Acquisition->Analog Output ( for Analog Output Operations); and Search Examples->I/O Interfaces->Data Acquisition->Counters (for counter operations). Also; I'm including an Application Note which talks about synchronization of multiple DAQ tasks I think will be helpful for you also.
Regards.
Filipe
Attachments:
Advanced_Sync_Techniques_for_DAQ.pdf ‏189 KB

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When I use two flat sequences running in parallel inside my test loop, one to control the pulse timing, and the other to read the counters and do things with their results, it seems to work. In fact, Diff is always 0 or very occasionally the +/- 1 sequence. But in this case there is nothing controlling the relative timing such that the counters only get read after the pulse fires, though the results seem to show that this is true. I think the reads should be indeterminate with respect to the pulses, which would be unreliable. I don't know why it's working and can't expect it to work in other environments, can I? Moreover, if I set some of the pulse timing numbers to 1 or 2 or 5 ms, timeouts start happening again, too. So I think I have a workaround that I don't understand, shouldn't work, and shouldn't be trusted. See SeparateSequence.vi for this one.
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Attachments:
AfterPulse.vi ‏51 KB
InSeparateSequence.vi ‏49 KB

Kevin, thanks for all the work.
>Have you run with the little execution highlighting lightbulb on? -Yes. In versions of this where there is no enforced timing between the counter and the digital line, and there's a delay inserted before the digital line, it works. There are nearly simultaneous starts on two tracks. Execution proceeds directly along the task wire to the counter. Meanwhile, the execution along the task wire to the digital high gets delayed. Then, when the digital high fires, the counter completes its task, and execution proceeds downstream from the counter. Note, I do have to set the timeout on the counter longer, because the vi runs so slowly when it's painting its progress along the wires. If there is any timing relationship enforced between the counter and the digital transition, it doesn't work. It appears to me that to read a counter, you have to ask it for a result, then drive the line high, and then receive the result, and execution inside the counter has to be ongoing during the rising line edge.
>from what I remember, there isn't much to it. There really aren't many candidate places for trouble. A pulse is generated with DIO, then a single sample is read from each counter. -Yup, you got it. This should be trivial.
>A timeout means either that the pulse isn't generated or that the counter tasks don't receive it. - Or it could mean that the counter task must be in the middle of executing when the rising edge of the pulse arrives. Certainly the highlighted execution indicates that. Making a broken vi run by cutting the error wires that sequence the counter read relative to the pulse also seems to support that.
>Have you verified that the digital pulse happens using a scope? -Verified in some versions by running another loop watching a digital input, and lighting an indicator, or recording how many times the line goes high, etc. Also, in your vi, with highlighting, if I delete the error wire from the last digital output to the first counter to allow parallel execution, I see the counter execution start before the rising edge, and complete when the line high vi executes. Also, if I use separate loops to drive the line high and to read the counter, it works (see TwoLoops.vi or see the screenshot of the block diagram attached below so you don't need a LV box). I could go sign out a scope, but think it's obvious the line is pulsing given that all these things work.
>Wait! I think that's it! If I recall correctly, you're generating the digital pulse on port0/line0... On a 6259, the lines of port 0 are only for correlated DIO and do not map to PFI. -But I'm not using internal connections, I actually physically wired P0L1 (pin 66) to PFI0 (pin 73). It was port0/line1, by the way. And when running some of these vi's, I also physically jumper this connection to port0/line2 as an analog input to watch it. And, again, the pulse does cause the counter to operate, so it clearly connects - it just doesn't operate the way I think it is described operating.
For what it's worth, there's another mystery. Some of the docs seem to say that the pulse has to be applied to the counter gate terminal, rather than to the line associated with the sample clock source on the timing vi. I have tried combinations of counter gate and or sample clock source and concluded it seems like the sample clock source is the terminal that matters, and it's what I'm using lately, but for example the document I cited, "Buffered Event Counting", from last September, says "It uses both the source and gate of a counter for its operation. The active edges on the gate of a counter is used to latch the current count register value in a hardware register which is then transferred via Direct Memory Access...". I may go a round of trying those combinations with the latest vi's we've discussed.
Attachments:
NestedSequences.png ‏26 KB

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Want to trigger event count from both counters (E) to buffer using FOUT (100kHz/16 or slower) as a trigger

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