Reading a differential signal into the Kintex 7 KC705

I am attempting to read a differential signal into the FPGA: i_SCLK_P and i_SCLK_N. I want to trigger my ILA on a rising edge of i_SCLK. I am unable to contrain my pins correctly. I am getting the following error:
[Place 30-64] Illegal IOStandard configured for port 'i_SCLK_N'. I/O port 'i_SCLK_N' is differential, but has single-ended IOStandard value LVCMOS25.
I have then attempted to change my IOStandard to LVDS (which I have attached) but I then get the following error:
[Drc 23-20] Rule violation (BIVB-1) Bank IO standard Support - Bank 16 has incompatible IO(s) because: The LVDS I/O standard is not supported. Move the following ports or change their properties: i_SCLK_P
I have tried to change to a different bank twice now. I was hoping that I could find a bank with LVDS capability. I have looked through the KC705 datasheet and it appears that the pins that I am using should be valid.
Where am I going astray? Thanks for the help!

Hello ,
Which Vivado version are you using? Can you try in Vivado 2015.2
Does your design contains MIG core?
Also check if the following thread is helpful:
http://forums.xilinx.com/t5/7-Series-FPGAs/K7-problem-of-HR-BANK-LVDS-signals-selected/m-p/523965
--Syed
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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Reading a differential signal into the Kintex 7 KC705

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