Test of design with SDK.

Question

Hi ,
I did a design in vivado for a Bandpass Filter in Vivado . Now i want to test it in the ZedBoard with SDK.
i creat a customer block of this Filter . you can see the code in the attachments :
 the “fir.vhd” file has been integrated into the hierarchy because i have instantiated it from within the peripheral.
this is the added lines in fir_v1_0_S00_AXI.vhd:
   signal ergebnis : std_logic_vector(18 downto 0);  
    component FIRfilter  
    port (  
      clk: in std_logic;  
      x: in std_logic_VECTOR(15 downto 0);   
      y: out std_logic_VECTOR(18 downto 0));  
    end component; 
fir_0 : FIRfilter
    port map (  
      clk => S_AXI_ACLK,   
      x => slv_reg0(15 downto 0),  
      y => ergebnis);
    -- User logic ends
now  i want to test it in sdk and i have always the problem that the c-code  which i read it give me always a false  output.  simple multplikation of the new given Inputvalue  x without shifting the  old value , which will be normally multiplied with the next coefficient by the adding of a the new x value .
this is the c code :
    #include "platform.h"
    #include "xbasic_types.h"
    #include "xparameters.h"
Xuint32 *baseaddr_p = (Xuint32 *)XPAR_FIR_0_S00_AXI_BASEADDR;
double eingang[20] = {1,2,3,2,2,1,4,3,4,8,7,9,10,1,4,5,6,7,8,9};
    int main()
    init_platform();
   int i;
   for(i=0;i<20;i++) {
   // write input in register 0
       *(baseaddr_p+0) = eingang[i];
    xil_printf("Wrote: 0x%08x \n\r", *(baseaddr_p+0));
    // Read  output from register 1
    xil_printf("Read : 0x%08x \n\r", *(baseaddr_p+1));
    xil_printf("End of test\n\n\r");
    return 0;
the result !!!:
please i need help.
thanks
houssem

Answer 1

check this document
http://impulseaccelerated.com/uploads/3/3/7/7/3377898/microblazetutorials.pdf