Clock-in and Clock out timings in ESS

Hi,
My client want to display the Clock-in Clock-out timings recorded at the terminal (we are not using CATS) to be displayed in ESS portal.Pleae let me know where (in which node) and how to do this.
Thx
J

You can use Clock in clock out iview which is standard available in EHP5 too, It displays clock in events from Teven!
ie 2011 infotype
check here more
http://help.sap.com/erp2005_ehp_05/helpdata/en/25/340b0507434193adbfe3f8fc8896c7/frameset.htm
do the customisaiton in PTCOR trans code in backend!

Similar Messages

Is it possible to have Clock in and clock out times in weekly view

Hi,
We have Daily View and Weekly View in Record Working Time iview in ESS.We can set the Clock in and Clock out times in Daily view if we check the With Clock Times checkbox in Data Entry Profile.But we want to have same Clock in and Clock out in Weekly view without any developement.
If it not possible thru config how much will be the Development Effort
Thanks
Bala Duvvuri

Siddharth,
can you please elaborate this
Thanks
Bala Duvvuri

Is it possible to have clock in and clock out in weekly view

Hi,
We have Daily View and Weekly View in Record Working Time iview in ESS.We can set the Clock in and Clock out times in Daily view if we check the With Clock Times checkbox in Data Entry Profile.But we want to have same Clock in and Clock out in Weekly view without any developement.
If it not possible thru config how much will be the Development Effort
Thanks
Bala Duvvuri

Hi Bala
You can have clock in and clock out in a weekly view.
you have to change the data entry profile settings.
In general settings tab in data entry profile click the with clock times button and maintain the Period type to 02 in time settings tab.
And you can view the weekly entry in clock in and clock out.
Ravee
+91.99206.33669

Clock in and clock out issue

Hi All,
I am looking for a solution for the below issue. Please help me out
Clock in and clock out details from third party terminal are stored in SAP in IT2011.
My requirement is if the duration between first clock in and last clock out is less than 4 hours system should consider as LOP for that day.
can you please let me know if I should a PCR or any other way.
Regards
Vish

You can do as below:
Normally time type 0000 is used for normal attendance hrs in time schema PCR's like TP09, TP10, TP11.
Before CUMBT function, call a PCR using ACTIO to do as below:
If the daily value is time type 0000 < 4.00, insert a w/t for LOP absence hrs for the day. The hrs can be as per the business rules:
a)from IT 7 - provided IT 7 has the correct data from WSR and WSR is correct.
HRS=IDAHRS           daily hrs
or
HRS=IWEHRS HRS/5    weekly hrs/5
or
b)from the DWS for that day
HRS=S        -DWS hrs including any substitution
See example below assuming 0000 time type for normal attendance hrs, 8001 time w/t for LOP hrs.
             D   HRS=D0000    HRS?4
<                HRS=IDAHRS ADDZL8001
In payroll,
- Time w/t's from time eval are imported by ZLIT function (usually in XT00 sub schema).
- PCR XPPF and its sub PCRs this w/t hrs can be used to reduce the partial pay factors e.g. /801 used to reduce the payments like basic pay, etc.
- PCR XVAL uses these factor w/t's to reduce the payments.

Need support - Writing PCR (To find missing clock-in and clock-out)

Hi Gurus,
I need support on writing PCR on below scenario.
Scenario:
Need to determin missing clock-in and clock-out punches and generates LOP for the same.
Regards,
Raji

Hi,
In this case you need to build logic like the follow.
Assumptions: mulitiple time pairs are there.
First check employee present or not, then check data coming through time events or not then check first pair after that take HRS value as start time of first pair if yes store day balances in ABCD. in case of No check Last pair take end time store in as day balance BCDE. after that based on day balance values genearte wagetypes in another PCR.
Note: in same PCR you can store wage type aslo.

Time Report required to capture clock in and clock out.

Hi All,
We have requirement where in we need to present the following details in the report to the client:
1) Clock in
2) Clock out
3) PLanned working hours
Pls let me know if there is any standard report for the same or any sap query that can be copied and used.
We are using negative time management with the Time management status as 7.
Points would be awarded.
Thanks,
Deepali

Hi Deepali,
RPTCORDBVIEW (Display Clock-In/Out Corrections (Database)): You can use this report to view all information about the clock-in/out corrections that have been entered.
Could you please follow the link bellow for more the details:-
http://help.sap.com/erp2005_ehp_03/helpdata/EN/79/e71940a65ec442e10000000a1550b0/frameset.htm
Hope this info was helpful to you..
Regards,
Sagar.

Clock-in Clock-out corrections using ESS

Hi,
When we change the Time data using Clock-in, Clock-out corrections in ESS, it is not appearing in 2011 (Teven table). When will this, gets updated to the table and is there any tiem limit set for the updation ??
Thanks & Regards,
Vidhya T.R

On ESS, there will be optoin to run Time evaluation. Generally the update happens after the Time eval.
If this helps, pl do reward.
Thanks
Narasimha

Custom POD and Clock-In/Out

Dear Experts,
did someone face the problem with Custom PODs (Custom POD Plugin, changing the "manufacturing" path of POD to custom one) and Clock-In/Out?
When I turned the Auto Clock-In on on a custom POD, I can not reach the POD.
Ist this a bug or do I have to change something in the settings?
This occurs on SAP ME 6.1.4 Patch 38.
The error message is, that the POD could not be found. Does this something have to do with auto clock in, the redirect and a custom pod?
Regards,
Andrej

Hi Oksana,
thank you for your reply.
I simply have a custom POD plugin. Therefore, my POD does not use the standard "manufacturing" link, but a "custom_manufacturing".
I have configured shifts and labor tracking. The option to automatically clock in at log-in is enabled.
After I log in to ME, I recieve the notification of sucessfull clock in. But after I acess my custom POD with the "custom_manufacturing" link, I do get an "resource not found" error.
After I disable Clock-In at Log-On, I do not get this error.
If you need more detailed information, just point me to the direction you need, as of my view point the root cause is clear, as after disabling the option, everything works.
I do not have tested this with 15.0, so I do not know if this is ME 6.1.4 issue only.
Thnaks in advance.
Regards,
Andrej

Clock In/Out Correction in ESS,

Dear Gurus,
While Testing Clock In/Out Correction in ESS i got following error:
The date of the correction is outside the permitted processing period.
Please help me regarding this.
regards,
Surekha

Clock in clock corrections allows you to correct the error occured in Rptime, Please check the config in PTCOR
have you done the customisation? It should work no doubt

Clock in and Out - Negative TIm MGT

Hi FRds,
Can we maintin the Clock and clock out In Negative Time Management.
As of client is in Negative Tim MGt. .. But now i says that he wants to maintain the Clock in and Out From Time Recording System.
Please suggest for the above ..
Thanks & Regards
KRC.

Hi Sri,
In Positive Tim Can we capture the absenses without any Manuall Interaction.
Ex: 1) If the employee is absent for 2day, the quato is available for only 1 day. than the system should automatically has to be deduced one day under Quota and other as a LOP. Can this is be done ( automatically)
Can u plz update me with some documents or link which helps in Configuring this Postive Tim.
What are the steps to be considered before staring '+ ive' TIM MGT Configuration.
Thanks in advance
KRC.

Clocking In and out

This is a different problem altoghether and I am kinda running out of ideas
I am trying to store date/time for a user when he/she edits a record. A date/time needs to be stored when the modified record is saved
I need to use this data and then find out the time spent by the user on that particular record.
This clocking in and out on the record can happen multiple times by a user during a day.
I need to store the date/time the user starts editing the data as well as the date/time the user saves the modified record
Any suggestions?
Edited by: user612663 on Oct 23, 2008 12:44 AM

Thanks for the reply Bob,
This was solution which was actually rejected as the user might visit and modify the record many times and too many tasks would be created.
I was wondering if we could create a custom field named start time and end time on one task and it keeps on updating itself and in some way the historical data can be reported??
Nick

Buffered event counting. Why can't I explicitly sequence generating the Sample Clock Pulse and reading the counters?

At irregular occasions I need to grab counts from several counters, and buffering the counts must be done simultaneously for all counters. I'm modeling my approach after zone.ni.com/devzone/cda/tut/p/id/5404 which someone kindly pointed out in an earlier thread. However, that example only uses one counter, and you can't test the synchronization with only one counter, so I am using two counters configured the same way, and they're wired to a single benchtop signal generator (for example at 300 kHz).
What I want to do, I can test in a loop with a somewhat random wait in it. I want to drive a hardware digital output line high for a few ms and then low again. The hardware line is physically connected to terminals for my timing vi's Sample Clock Source and so will cause them to buffer their counts for later reading. After I pulse this line, when I know new good buffered counts await me, I want to read both my counters. If their bufferings are simultaneous, then each counter will have counted the same number of additional counts since the last loop iteration, which I can check by subtracting the last value sitting in a shift register and then subtracting the two "additional counts" values and displaying this difference as "Diff". It should always be 0, or occasionally +1 followed immediately by -1, or else the reverse, because buffering and a count could happen practically at the same moment.
When I do this using a flat sequence to control the relative timing of these steps, so the read happens after the pulse, the counters often time out and everything dies. The lengths of time before, during, and after the pulse, and the timeout value for the read vi, and the size of the buffer and various other things, don't seem to change this, even if I make things so long I could do the counting myself holding a clipboard as my buffer. I've attached AfterPulse.vi to illustrate this. If I get 3 or 10 or so iterations before it dies, I observe Diff = 0; at least that much is good.
When I use two flat sequences running in parallel inside my test loop, one to control the pulse timing, and the other to read the counters and do things with their results, it seems to work. In fact, Diff is always 0 or very occasionally the +/- 1 sequence. But in this case there is nothing controlling the relative timing such that the counters only get read after the pulse fires, though the results seem to show that this is true. I think the reads should be indeterminate with respect to the pulses, which would be unreliable. I don't know why it's working and can't expect it to work in other environments, can I? Moreover, if I set some of the pulse timing numbers to 1 or 2 or 5 ms, timeouts start happening again, too. So I think I have a workaround that I don't understand, shouldn't work, and shouldn't be trusted. See SeparateSequence.vi for this one.
I also tried other versions of the well-defined, single sequence vi, moving the counter reads to different sequence frames so that they occur with the Sample Clock Source's rising edge, or while it is high, or with the falling edge, and they also often time out. I'll post these if anyone likes but can't post now due to the attachment limit.
Here's an odd, unexpected observation: I have to sequence the reads of the counters to occur before I use the results I read, or else many of the cycles of this combine a new count from one counter with the one-back count from the other counter, and Diff takes on values like the number of counts in a loop. I though the dataflow principle would dictate that current values would get used, but apparently not so. Sequencing the calculations to happen after the reads fixes this. Any idea why?
So, why am I not succeeding in taking proper control of the sequence of these events?
Thanks!!!
Attachments:
AfterPulse.vi ‏51 KB
InSeparateSequence.vi ‏49 KB

Kevin, thanks for all the work.
>Have you run with the little execution highlighting lightbulb on? -Yes. In versions of this where there is no enforced timing between the counter and the digital line, and there's a delay inserted before the digital line, it works. There are nearly simultaneous starts on two tracks. Execution proceeds directly along the task wire to the counter. Meanwhile, the execution along the task wire to the digital high gets delayed. Then, when the digital high fires, the counter completes its task, and execution proceeds downstream from the counter. Note, I do have to set the timeout on the counter longer, because the vi runs so slowly when it's painting its progress along the wires. If there is any timing relationship enforced between the counter and the digital transition, it doesn't work. It appears to me that to read a counter, you have to ask it for a result, then drive the line high, and then receive the result, and execution inside the counter has to be ongoing during the rising line edge.
>from what I remember, there isn't much to it. There really aren't many candidate places for trouble. A pulse is generated with DIO, then a single sample is read from each counter. -Yup, you got it. This should be trivial.
>A timeout means either that the pulse isn't generated or that the counter tasks don't receive it. - Or it could mean that the counter task must be in the middle of executing when the rising edge of the pulse arrives. Certainly the highlighted execution indicates that. Making a broken vi run by cutting the error wires that sequence the counter read relative to the pulse also seems to support that.
>Have you verified that the digital pulse happens using a scope? -Verified in some versions by running another loop watching a digital input, and lighting an indicator, or recording how many times the line goes high, etc. Also, in your vi, with highlighting, if I delete the error wire from the last digital output to the first counter to allow parallel execution, I see the counter execution start before the rising edge, and complete when the line high vi executes. Also, if I use separate loops to drive the line high and to read the counter, it works (see TwoLoops.vi or see the screenshot of the block diagram attached below so you don't need a LV box). I could go sign out a scope, but think it's obvious the line is pulsing given that all these things work.
>Wait! I think that's it! If I recall correctly, you're generating the digital pulse on port0/line0... On a 6259, the lines of port 0 are only for correlated DIO and do not map to PFI. -But I'm not using internal connections, I actually physically wired P0L1 (pin 66) to PFI0 (pin 73). It was port0/line1, by the way. And when running some of these vi's, I also physically jumper this connection to port0/line2 as an analog input to watch it. And, again, the pulse does cause the counter to operate, so it clearly connects - it just doesn't operate the way I think it is described operating.
For what it's worth, there's another mystery. Some of the docs seem to say that the pulse has to be applied to the counter gate terminal, rather than to the line associated with the sample clock source on the timing vi. I have tried combinations of counter gate and or sample clock source and concluded it seems like the sample clock source is the terminal that matters, and it's what I'm using lately, but for example the document I cited, "Buffered Event Counting", from last September, says "It uses both the source and gate of a counter for its operation. The active edges on the gate of a counter is used to latch the current count register value in a hardware register which is then transferred via Direct Memory Access...". I may go a round of trying those combinations with the latest vi's we've discussed.
Attachments:
NestedSequences.png ‏26 KB

MyRIO memory, data transfer and clock rate

Hi
I am trying to do some computations on a previously obtained file sampled at 100Msps using myRIO module. I have some doubts regarding the same. There are mainly two doubts, one regarding data transfer and other regarding clock rate.
1. Currently, I access my file (size 50 MB) from my development computer hard drive in FPGA through DMA FIFO, taking one block consisting of around 5500 points at a time. I have been running the VI in emulation mode for the time being. I was able to transfer through DMA from host, but it is very slow (i can see each point being transferred!!). The timer connected in while loop in FPGA says 2 ticks for each loop, but the data transfer is taking long. There could be two reasons for this, one being that the serial cable used is the problem, the DMA happens fast but the update as seen to the user is slower, the second being that the timer is not recording the time for data trasfer. Which one could be the reason?
If I put the file in the myRIO module, I will have to compile it each and every time, but does it behave the same way as I did before with dev PC(will the DMA transfer be faster)? And here too, do I need to put the file in the USB stick? My MAX says that there is 293 MB of primary disk free space in the module. I am not able to see this space at all. If I put my file in this memory, will the data transfer be faster? That is, can I use any static memory in the board (>50MB) to put my file? or can I use any data transfer method other than FIFO? This forum (http://forums.ni.com/t5/Academic-Hardware-Products-ELVIS/myRIO-Compile-Error/td-p/2709721/highlight/... discusses this issue, but I would like to know the speed of the transfer too.
2. The data in the file is sampled at 100Msps. The filter blocks inside FPGA ask to specify the FPGA clock rate and sampling rate, i created a 200MHz derived clock and mentioned the same, gave sampling rate as 100Msps, but the filter is giving zero results. Do these blocks work with derived clock rates? or is it the property of SCTL alone?
Thanks a lot
Arya

Hi Sam
Thanks for the quick reply. I will keep the terminology in mind. I am trying analyse the data file (each of the 5500 samples corresponds to a single frame of data) by doing some intensive signal processing algorithms on each frame, then average the results and disply it.
I tried putting the file on the RT target, both using a USB stick and using the RT target internal memory. I thought I will write back the delay time for each loop after the transfer has occured completely, to a text tile in the system. I ran the code my making an exe for both the USB stick and RT target internal memory methods; and compiling using the FPGA emulater in the dev PC VI. (A screenshot of the last method is attached, the same is used for both the other methods with minor modifications. )To my surprise, all three of them gave 13 ms as the delay. I certainly expect the transfer from RT internal memory faster than USB and the one from the dev PC to be the slowest. I will work more on the same and try to figure out why this is happening so.
When I transferred the data file (50MB) into the RT flash memory, the MAX shows 50MB decrease in the free physical memory but only 20MB decrease in the primary disk free space. Why is this so? Could you please tell me the differences between them? I did not get any useful online resources when I searched.
Meanwhile, the other doubt still persists, is it possible to run filter blocks with the derived clock rates? Can we specify clock rates like 200MHz and sampling rates like 100Msps in the filter configuration window? I tried, but obtained zero results.
Thanks and regards
Arya
Attachments:
Dev PC VI.PNG ‏33 KB
FPGA VI.PNG ‏16 KB
Delay text file.PNG ‏4 KB

You tube and clock

Since I updated to IOS6 last week i have had a few problems.
1 i seem to have completely lost my Youtube icon,
2 it seems unless i just never noticed it, i now have a CLOCK icon, which is fine but not sure where it came from
3 my maps do not seem to be working as before with streetview available when i find an address
Any ideas? re the Youtube, i saw someone talking about a trial and opting out of it, so i have .
Thanks

YouTube is now gone in iOS 6 as is the Google Maps app. Apple has replaced the Google maps App with its own Maps App and they are continuing to work on it. Ther is a mobile Google Maps app with Street view now.
Read this for more information about the Google Mobile Maps Web App.
http://appleinsider.com/articles/12/10/04/street-view-for-google-maps-web-app-go es-live-for-some
The clock is new in iOS6.

Mouse, keyboard and clock freezing

Hello
My mouse, keyboard and clock are randomly freezing and I have to power off. Restart and it is fine for awhile. Went to the Genius Bar and couldn't recreate it of course. Created a new user account but it happens there also. So annoying. Have read on the boards and google that other people have had the same issue but can't find a solution. Help? Running Snow Leopard

Quote
Corsair said that setting the Failsafe Defaults and setting XMP to enabled should work.
As I said before, XMP Settings (DDR3-1600/CL8) are overclocking settings, not default settings. Corsair does not (actually cannot) reallly guarantee that these settings are stable. To point that out, I quoted the standard note that Corsair has put into the datasheet for your modules.
The native settings (industry standard settings) for your modules are DDR3-1333 @9-9-9-24 @1.5 +/- 0.075V. I already provided you with a link to the datasheet which lists these parameters. That is why I suggested to use these. Have you tried these settings yet?
Quote
It seems like the BIOS settings for their RAM is a trade secret and heavily guarded
Not really. They are in the datasheet.
If the DDR3-1333 settings do not change anything, reduce the memory clock speed to DDR3-1066. That is the maximum clock speed the memory controller of your processor natively supports (according to Intel Specifications).
Please keep Spread Spectrum disabled at all times.
Quote
Does anyone know what settings in the BIOS I have to set so the RAM runs at 1.5v?
The JEDEC Standard SPD Settings for your memory modules are in the Corsair Datasheet. I have already pointed them out twice.
Quote
Also I've noticed that the IOH temperature has been running around 60 - 70 degrees C.
The maximum allowable temperature for the IOH is around 100°C (according to Intel Specs). As long as the temperature stays below that value, there should be no functional issues. To double check: Point an extra fan to the IOH heatsink to provide additional cooling and see if that changes anything.
One more thing:
What is your current BIOS Version?

Clock-in and Clock out timings in ESS

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