Connect digital analog ground

Greetings.
I have a mixed-signal Multisim design which I have forward annotated to Ultiboard. My Multisim circuits use 2 different grounds - net 0 and net DGND. For simplicity, I would like to prototype a first version of the boards with the grounds logically connected, so I don't need to worry about ground loops being created by the fact that I'm using separate digital and analog lab supplies.
I have checked the box in Multisim under "Sheet Properties -> PCB -> Connect digital ground to analog ground." I have transferred my design to Ultiboard 11 and specified a 4 layer board. Layer 3 is my ground plane, with a large copper area connected to Net 0. While placing components and vias on my board, I'm noticing that the thru-holes and vias I define as connected to Net 0 appear as I expect - with the "+" thermal relief on layer 3. However, vias logically connected to DGND are appearing on layer 3 with large areas of copper removed (I've specified 12 mils clearance on each copper layer). If I change the copper area on layer 3 to net DGND, instead of net 0, I notice the reverse situation. All of my analog ground vias and thru-holes have copper cleared away, and the DGND vias are now filled.
I don't believe a logical connection exists between net 0 and DGND in the forward annotated netlist. Is there some way I can confirm this? Did I miss a step in the process while trying to connect these two?

Thank you for your reply, Mark.
I was going to upload my Multisim project file, but then realized a lot of my components are now in my Corporate Database, so I can keep vendor and manufacturer-specific part numberings and inventory quantities all together in the same place. Instead, I took some screenshots and created a .pdf file. I uploaded the pdf file to transferbigfiles.com, here.
First, I snipped some sections of my design to illustrate the current state of things. On the first page, you can see that my default sheet properties are setup such that digital and analog grounds should be connected. I have an FMC-LPC connector "J17" in my design, with the "DGND" wired to it. The J17B pin actually represents about 40 different SMD pads on a VITA 57 connector. The DGND component is from the Master Database under Power Sources, though I think I renamed it from "DGND" to "GND." As you can see, Ultiboard is showing a lot of DRC errors right now because the vias are set to assume net "0" while the SMD pads were exported as connected to net DGND.
Next page, I unchecked the box "Connect digital ground to analog ground" and forward annotated the changes. Ultiboard found no differences.
Next I thought that perhaps my renaming of the default Refdes from "GND" to "DGND" could be the problem. So I went through my design and replaced all of my "DGND" triangles with the DGND component from the Master Database. As you pointed out, though the component is named "DGND" the Refdes is actually "GND." I left the sheet properties as is, with digital /analog grounds not connected. When I forward annotate the changes, I observe what I expect - the DGND connections are removed and replaced with GND connections. (Next page) The SMD pads are now logically connected to the net named GND instead of DGND.
Finally, I went back to Multisim and tried combining the nets "GND" and "0" automatically by selecting the check box in Sheet Properties. Unfortunately, when I forward annotate, Ultiboard detects no changes.
Following are 2 relevant sections of my .ewnet file I opened in a text editor, after my latest changes.
(net "0"
(trackwidth "6.00000000e+000")
(trackwidth_max "3.93700787e+002")
(trackwidth_min "6.00000000e+000")
(clearance_to_trace "6.00000000e+000")
(clearance_to_pad "6.00000000e+000")
(clearance_to_via "6.00000000e+000")
(clearance_to_copper "6.00000000e+000")
(routing_layer "1111")
(net_GUID "{8704ACB4-9808-4086-9C22-02206D379B13}")
(net "GND"
(net_GUID "{8EFCFB7F-F038-4362-A59D-667354159F44}")
Message Edited by pcurt on 02-22-2010 10:48 AM

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