Connexion cRIo perdu, fermeture FPGA

Bonjour,
Ce projet est l'exemple 'Servo Position Loop', adpater avec les slots (NI9263 et NI9411)que je possèdes sont mon cRIO NI Rio-9024 sur le chassis FPGA 9116.
Le programme s'exécute correctement sur la cible. Par contre lorsque que je termine le programme, cRIO se déconnecte. Je ne peux donc plus relancer le programme, à moins de rebooter le cRIO via Measure Automation.
Pourquoi ce programme ferme t-il la connection lorsqu'il s'arrete?
J'ai joins le projetqui pose souci.
Ci dessous le message d'erreur recu lorsque je tenté de redéployer l'application. Aucunes des solutions proposées n'a abouti.
Massif
Pièces jointes :
Control moteur test.zip ‏2144 KB

Bonjour,
L'erreur vient de la fermeture du vi "Trajectory generator VI".
Quand j'enlève ce VI, je ne perds pas la connexion avec mon cRIO.
On ne peut pas voir le code du VI et on ne peut pas le configurer.
Qlq sait comment fermer l'axe san perdre la connexion?
Ci-joint l'image du VI.
Massif
Pièces jointes :
Trajectory generator delete.JPG ‏119 KB

Similar Messages

How to read USER1 DIP-switch status of a cRIO chassis from FPGA?

How can I read the status of the DIP switches on a cRio chassis from the FPGA?
I am working with a cRIO 9022.. My idea is to set the system into a "service" mode by setting the USER1 switch to ON and communicate with the FPGA via the FPGA-GUI(VI) on the host computer instead via the RT module which is used under normal conditions.
Any ideas? Unfortunately, I do not have an unused channel left ...and (as far as I know) can't use the RS232 from the FPGA.
Many thanks in advance,
Luke
Solved!
Go to Solution.

Hi, this is the correct information. You cannot read from the FPGA the DIP switch status. The only thing you could do is to use the Read Switch.vi function located under Functions -> Real Time -> RT utilities palette
This is how you probably know only for the RT Host side and not the FPGA.
Regards Anoj
Anoj Mubarak
National Instruments

Binary to Voltage Conversion of encoder data on cRio 9073 using FPGA

I am using FPGA with a cRio 9073 to acquire torque and absolute quadrature encoder values. It says in the FPGA instructions that the documentation for the 9073 should include the binary to voltage conversion, but when I looked at the documentation, it wasn't there. Where can I find the conversion value or function to convert binary encoder data back to voltage? The encoder is hooked up to an analog converter and is acquired with a 9215 AI (+-10V differential). Thanks

There are individual formulas for one or a group of modules.
LabView examples path:
LabVIEW 2010\examples\CompactRIO\Basic IO\Analog Raw Host Calibration\AI Raw Host Calibration
LabView help topic
Converting and Calibrating CompactRIO Analog Input Values (FPGA
Interface)
Best regards
Christian

Continuous Data Logging with NI 9236 an cRIO 9076 with FPGA

Hey all,
i'm a beginner in LabVIEW/FPGA. My goal is it to
continuous acquire and log data. I've a 9236, CH0 is
connected to a strain gauge and the cRIO 9076.
I've written a code and I see the incoming data on the FPGA.vi.
On the Host.vi there is no outcoming data out of the FIFO.
There is no error messages or an error during the compilation.
Do I have a timing problem? Where ist the big mistake
Thank you!
Attachments:
1.jpg ‏98 KB
2.jpg ‏71 KB
4.jpg ‏337 KB

In your first image one problem is that you are starting the module on each iteration of the loop. I can't tell how your FIFO is configured, but take a look at the example "Hardware Input and Output->CompactRIO->Module Specific IO->Analog Input->NI 923x Continuous DMA.pvproj. I don't know which LabVIEW version you are using but I found this example in 2012.

Connexion cRIO 9073

Bonjour.
Après de nombreuses tentatives, je n'arrive pas à faire reconnaitre mon cRIO 9073 sur le logiciel MAX. J'ai bien configurer l'adresse IP de l'ordinateur pour qu'elle soit compatible avec mon cRIO. Le logiciel ne trouve pas l'appareil... (j'arrive pourtant à le voir avec un "ping" sur un terminal)
J'utilise MAX 5.5. Est-ce dû à une non compatibilité ?
Merci d'avance
Simon M.

Hey Simon,
Try going through the steps in this document. There are a lot of steps in that document, but if you follow them closely it will almost certainly resolve your issue.
Can you also please post a Max technical report (instructions here).
Let us know if you are still having trouble after going through that document.
Thanks!
-Sam K
LabVIEW Hacker
Join / Follow the LabVIEW Hacker Group on google+

Alternative to DMA transfers from Host to FPGA in cRIO 9004

Hi,
We are using a cRIO 9004 + 9104 FPGA Chassis + 8x NI 9505 modules to replace an 8 axis Scorbot educational robot controller by a cRIO, but we found some troubles:
- We are using FPGA IPs for Encoder reading, PWM signal generation and PID control, for the 8 axis. This is done using 3 SCTLs for each axis: one SCTL for encoder reading, one for PWM generation and one for NI Softmotion Splines and PID position control.
The FPGA VI is successfully deployed.
- We are using the NI Soft motion in the Real Time controller for trajectory generation and user interface. We are not using another VI on the Windows PC for user interface, just the Real Time processor.
Here we get the R-T error -63001 (NI RIO FPGA Communications) when deploy the Real Time VI. It seems that our controller doesn't support DMA transfers from the Host to the FPGA.
Questions:
- If we cannot use DMA transfers from Host to FPGA, is there any other way to communicate the Host to the FPGA avoiding the R-T error -63001?
- Is a good idea to use indexed IPs to reduce the amount of SCTLs in the FPGA to just 3 (instead of 24 SCTLs)?
- Do you have any suggestion?
Regards,
Manuel

Hey there.
Indeed cRIO 900x series does not support DMA transfers from the Host to the FPGA; that is the reason you are getting an error 63001.
However it does support data transfer from the FPGA to the Host You can find that information in this KB.
To transfer information from the host to the rt and to the fpga you can use:
Host <--> RT
Network shared variables
TCP
UDP
Data socket
RT --> FPGA
Front panel communication
FPGA -->RT
User defined variables
Direct memory access
DMA FIFOs
I added some links with examples of each type of communication
Hope this info helps
Good luck

FPGA problems on cRIO 9004

So, Ive been playing with a cRIO-9004 with FPGA. But there is a problem, everytime I place an FPGA I/O node onto the block diagram it does not work.
it outputs a null signal and says this in context help "LabVIEW does not support I/O nodes in the My Computer application instance. Place the node on the block diagram of a VI that is open under an appropriate target in the Project Explorer window."
I do not have it within the my computer instance. I have done this before with a sbRIO and followed similar steps. I have never had this problem with the sbRIO.
Any ideas?
Solved!
Go to Solution.

Under your main project you need to have added a "cRIO target" underneath that target, you need to have added a "cRIO chassis". And then udnerneath the chassis you need to have added an "FPGA Target". Finally, you place your VI inside the "FPGA target" in the tree structure. To add something, usually right-clicking on the item it is going to give you an option to add->target or something similar.

Servo motor control using CRIO+FPGA and 9477 digital out module

Hello experts,
I have a futaba BLS551 brushless motor digital servo (3 wires-+,-, signal). i also have a CRIO+real-time+fpga and 9477 digital out module. how can i generate servo signals using this module
please help...
Thanks,

freemason,
In order to control your servo motor with the FPGA and or DIO module you will have to write drivers to control your motor and drive. While this is possible is an extremely complicated and time consuming process. I would highly recommend you consider using the NI 9514 with soft motion as it will provide full servo functionality and is relatively easy to use.
Regards,
Sam K
Applications Engineer
National Instruments

Fuzzy Controller on cRIO FPGA

Hi,
I am trying to implement a fuzzy controller on the cRIO 9073 in FPGA mode. My problem is that there is not even the a symbol of fuzzy controll to drag and drop. Are there any possibilities to do that?
I have already implemented the controller in scan mode. However, I want to implement it in FPGA mode to get higher performance.
Michael

Hi Michael
You're right the fuzzy controller VIs are not shown under FPGA. The Fuzzy Controller VIs are implemented for
Windows or Real-Time. (They use DBL as data type which is not supported under FPGA)
It is possible to implement a Multi-Channel PID with the PID Express VI under your FPGA target. For more
information see at these two links.
PID and Fuzzy Logic Toolkit User Manual
http://www.ni.com/pdf/manuals/372192d.pdf
Using PID on FPGA Targets (PID and Fuzzy Logic Toolkit)
http://zone.ni.com/reference/en-XX/help/370401J-01/lvpidmain/pid_on_fpga/
Kind regards,
Andreas Scheuber
Applications Engineer
NI Switzerland

Fpga DMA FIFO compilation error

Hello,
I have a cRIO 9074 with FPGA. I am trying a simple piece of code to learn how to aquire data that is generated on the FPGA at a rate of 10 KHz and transfer it to the Host VI for processing it later offline. However, I encounter this compilation error when compiling this basic FPGA VI containing a FIFO
write node (picture of the VI attached below). In the Compilation Report, it says that there were 256 Block RAMs used (the
total number is 40), therefore an error was produced. The exact compilation error
notification from the Xilinx report is reproduced below:
# Starting program map
# map -o toplevel_gen_map.ncd -intstyle xflow -timing toplevel_gen.ngd
toplevel_gen.pcf
Using target part "3s2000fg456-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
ERRORack:2310 - Too many comps of type "RAMB16" found to fit
this device.
ERROR:Map:115 - The design is too large to fit the device. Please check the Design Summary section to
see which resource requirement for your design exceeds the resources available
in the device. Note that the number of slices reported may not be reflected
accurately as their packing might not have been completed.
NOTE: An NCD file will still be
generated to allow you to examine the mapped design. This file is intended for evaluation use only,
and will not process successfully through PAR.
Mapping completed.
See MAP report file "toplevel_gen_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
Number of errors : 2
Number of warnings : 125
ERROR:Xflow - Program map returned error code 2. Aborting flow
execution...
Bitstream Not Created
Timing Analysis Passed
What does this mean? How can I fix this error?
Thank you,
Bogdan
Solved!
Go to Solution.
Attachments:
FPGA.png ‏16 KB

Sorry, I forgot to mention that...LAbVIEW 2009. And yes, this is the only loop on the FPGA.vi. I just made up this code to understand how exactly I would save some data on the host for subsequent processing, but I didn't get to that point because the VI on the FPGA does not compile successfully. Do you know of any example of the most basic code for DMA FIFOs between the FPGA and Host Computer? This should be pretty straight forward, but for some reason it's not.
Thanks,
Bogdan

CRIO user LED does not seem to work!!

The LED shows up as a digital line output in my LV project, and shows
up in the FPGA I/O node (along with all the other I/O I have
configured), but I can't seem to get it to do anything. I've been able
to successfully compile a variety of different VIs targeted to the FPGA
and run them, but I cannot get the FPGA user LED to turn on-off.
I'm using LV 8.0.1 on Windows XP. I've tried 3 different cRIO 9004
controllers, and all of them seem to behave identically. I just created
a VI that measures the chassis temp and sets the LED status (on/off
alternating) every 0.5 seconds. The chassis temp measures just fine.
The LED never changes. I wired the error out (FPGA I/O node) to an
indicator, No error.
What am I doing wrong? Am I under the mistaken impression that I can control the On/Off status of the user LED?
Thanks,
The Dog

The "User LED" on the controller can only be written to using LabVIEW RT. The "FPGA LED" channel is currently only supported on the cRIO-9052 controller. That controller has both the "User LED" and "FPGA LED" on it's face. The cRIO-9002/4 controllers do not have the "FPGA LED". Since the chassis can be connected to any cRIO controller, the FPGA LED channel is always an available LabVIEW FPGA I/O resource.
Message Edited by Ruhmann on 07-06-2006 11:28 AM

IRQ from FPGA delay

Hi.
I have encoutered a problem in my code:
I am using a cRIO 9012 with FPGA utilize a NI 9871 4-port RS-485 module.
My code is using FPGA code and low-level communication VI's from this example:
http://zone.ni.com/devzone/cda/epd/p/id/6166
In my application i communicate through the NI9871, using the FPGA. The communication seems to work, but i am experiencing some unexpected delays.
The delay seems to appear at the "Wait on IRQ" invoke method in "901x 9871 DMA Read (Sub)" (see attached code). The FPGA code sets this IRQ when the current operation has completed. But i am experiencing unreasonable long delays here. (10+ mS).
I tested it without waiting for the IRQ and this gave me a delay of 1 mS on every attempt. And still i got valid data.
So it seems like the IRQ is held longer than necessarry.
In my application time is critical. The length of the incoming telegrams is fixed.
Thank you for your help.
Attachments:
code.zip ‏461 KB

ok hereare the project files i changed the fpga vi a bit and attached a print screen of the new error occuring i just want to transfer simple data and recieve them to my shift register
Attachments:
delayprob.jpg ‏90 KB
dmatry.zip ‏71 KB

FFT on LabVIEW FPGA

Hello Everyone,
I am doing a project in which i have to done FFT on data on LabVIEW FPGA. The data is actually a pixel value of an image which are first converted to imaginary parts and then their exponential is to computed, after taking exponential their FFT is to perform. I am new to Labview FPGA but know something about LabVIEW. If any one can guide me from where to start and how to do this, it will be of great help to me. I studied a tutorial on NI website but didn't get much out of it. I have NI cRIO-9024 LabVIEW FPGA. Any help will be appreciated.
Thanks
Regards

Hello!
We don’t have any finished VI’s shipping with the LabVIEW FPGA Module that does FFT. However if you can VHDL or have access to HDL IP Cores you are able to make use of the HDL node and implement it yourself. Then tests needs be to done in order to find if the VI can execute fast enough. If you search on HDL node on our website you will find more information about how to implement code using that function. You can also provide information to our R&D that you would like to see this feature in the future here:
http://digital.ni.com/applications/psc.nsf/default?OpenForm&temp1=&node=
Regards,
Jimmie Adolph
Systems Engineer Manager, National Instruments Northern Region
Bring Me The Horizon - Sempiternal

My cRIO (9022 , chassis 9113, module NI 9225)

Hello, I hope you are doing great
I create a new project that detects my cRIO (9022 , chassis 9113, module NI 9225) and I copied cRIO both the FPGA VI and Host of the original project NI but problem persists: there appeared another error message at the Host.VI (see attached file).
I did not get to solve this problem can you help me to find a solution as soon as possible
thank you for advance for your help
Attachments:
erreur1.jpg ‏276 KB
erreur2.jpg ‏214 KB

Hi basmasag,
It looks like you need to specify a top level VI of the Build Specification you're trying to build. You'll need to select the Source Files Category on the left in the build specification properties menu. Then highlight your top level VI (in the example its called NI 9225 Getting Started (FPGA).vi) and select the blue arrow to set it to be the Top-Level VI. I've included and image to better illustrate what I mean.
I think the FIFO error your seeing may be due to the Type of FIFO you've configured the Data FIFO to be in your project. In the example it was Tartget to Host - DMA. Make sure that's set correctly by double clicking on the Data FIFO, and setting the type. The second picture I attached should better demonstrate what I mean.
It seems like you may be new to LabVIEW FPGA, I think you'll find a lot of useful information here: http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgahelp/fpga_getting_started/
Applications Engineer
National Instruments
CLD Certified
Attachments:
Top-Level.png ‏59 KB
fifo.png ‏48 KB

RT & FPGA Modules – I am missing a fundamental concept

Recently I have been asked to program a compactRIO 9074 and in the midst of researching how to do that, I have become thoroughly confused…
I understand that the RT module is used for precise timing (i.e low jitter) and somehow it interfaces with the host computer (i.e. computer with the VI). I also understand the FPGA module allows you to, and forgive the simplicity, recreate the circuit on the chip, thus allowing virtually true multithreading and really fast speeds. Also, the FPGA interacts with the IO modules/ports.
The thing that I am unclear about is:
When you program the compactRIO 9074, do you select only one module (RT, FPGA) and ignore the other?
-or-
Do you use both modules - the RT module for the embedded hardware and the FPGA module for the FPGA bitstream? If so, how does the embedded hardware talk to the FPGA? Is this something you have to manually program? Any literature/tutorials on this?
-or-
I’ve even read something to the effect- the embedded module gets programmed with the RT module when the cRIO boots up for the first time. If that’s true, then does RT module get used only that only time and all programming thereafter is done with the FPGA module? Is the one-time RT module provided by NI or is this something I would have to create?
I think that I am missing something so fundamentally simple that this whole project is becoming so unnecessarily complicated.
Thanks in advance for the help.
Joe T.

It is a bit complicated, but powerful and flexible. If your needs are simple, NI provides tools (such as the scan engine) so you may not need to get into all the details.
The cRIO is almost a full computer, running a dedicated, real-time operating system (either PharLap ETS or VxWorks, depending on your cRIO). On top of that, there's the LabVIEW runtime. That computer also contains an FPGA, similar to if you bought one of the NI PCI FPGA cards and installed it in your PC.
The FPGA talks to the processor in the cRIO. If you need full control over the FPGA, then you write that code yourself and use DMA FIFOs and front-panel controls to transfer data between the cRIO and FPGA. If you just need access to the IO, you can use the Scan Engine, as previously noted. You also need a way for the cRIO to talk to your computer. Again, you can write code yourself, or use the NI-provided tools such as network shared variables. If you don't need the cRIO to do anything other than act as an expensive data acquisition device, you can link a shared variable to an I/O channel and access it directly from your PC, or share your IO variables over the network. Run a search on the NI site for "network shared variable scan engine" for more information.
You write separate code for the cRIO and the FPGA. You can run your VIs on the cRIO within the LabVIEW development environment and use most of the standard debugging tools, it will just be a bit slower to respond than when the LabVIEW code runs on your PC. When you have a working program, you can build an application and deploy it to the cRIO so that it will run at startup. You can do this as many times as you like. The LabVIEW program on the cRIO may contain an FPGA bitstream embedded in it. Writing code for the FPGA is more complicated - there are limitations, and you must compile the code before you can run it (no interactive debugging unless it's running in simulation).

Connexion cRIo perdu, fermeture FPGA

Similar Messages

Maybe you are looking for