Fpga DMA FIFO compilation error

Hello,
I have a cRIO 9074 with FPGA. I am trying a simple piece of code to learn how to aquire data that is generated on the FPGA at a rate of 10 KHz and transfer it to the Host VI for processing it later offline. However, I encounter this compilation error when compiling this basic FPGA VI containing a FIFO
write node (picture of the VI attached below). In the Compilation Report, it says that there were 256 Block RAMs used (the
total number is 40), therefore an error was produced. The exact compilation error
notification from the Xilinx report is reproduced below:
# Starting program map
# map -o toplevel_gen_map.ncd -intstyle xflow -timing toplevel_gen.ngd
toplevel_gen.pcf
Using target part "3s2000fg456-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
ERRORack:2310 - Too many comps of type "RAMB16" found to fit
this device.
ERROR:Map:115 - The design is too large to fit the device. Please check the Design Summary section to
see which resource requirement for your design exceeds the resources available
in the device. Note that the number of slices reported may not be reflected
accurately as their packing might not have been completed.
NOTE: An NCD file will still be
generated to allow you to examine the mapped design. This file is intended for evaluation use only,
and will not process successfully through PAR.
Mapping completed.
See MAP report file "toplevel_gen_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
Number of errors : 2
Number of warnings : 125
ERROR:Xflow - Program map returned error code 2. Aborting flow
execution...
Bitstream Not Created
Timing Analysis Passed
What does this mean? How can I fix this error?
Thank you,
Bogdan
Solved!
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Attachments:
FPGA.png ‏16 KB

Sorry, I forgot to mention that...LAbVIEW 2009. And yes, this is the only loop on the FPGA.vi. I just made up this code to understand how exactly I would save some data on the host for subsequent processing, but I didn't get to that point because the VI on the FPGA does not compile successfully. Do you know of any example of the most basic code for DMA FIFOs between the FPGA and Host Computer? This should be pretty straight forward, but for some reason it's not.
Thanks,
Bogdan

Similar Messages

How to decide the maximum number of elements for DMA FIFO in R series FPGA

Greetings!
I'm working on a project with NI R series PCIe-7842R FPGA board. To achieve fast data transfer I'm using target-to-host DMA FIFO. And to minimize the overhead, I'd like to make the FIFO size as large as possible. According to the manual, 7842R has 1728 kb (216KB) embedded block RAM, i.e., 108,000 I16 type FIFO elements available in theory (1728,000/16). However the FPGA had compilation error when I requested such amount of elements. I checked the manual and searched online but couldn't find the reason. Can anyone please explain? And in general, what's the max FIFO size given the size of the block RAM?
Thanks!

Hey iron_curtain,
You are correct that moving larger blocks of data can lead to more efficient utilization of the bus, but that's almost certainly not the most important factor here. Assuming of course that the FIFO on the FPGA is big enough to avoid overflows, I'd expect the dominant factor to be the size of read performed on the host. In general, larger reads on the host lead to improved throughput, up to the speed of the bus. This is because FIFO.Read is a relatively expensive software operation, so it's advantageous to make fewer calls to get the same amount of data.
Note that the larger your call to FIFO.Read the larger the host buffer needs to be. Depending on your application, it might need to be several times larger than the read size. You can set the buffer size with the FIFO.Configure node.
http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_dma_how_it_works/ explains the various buffers involved. It's important to note that the DMA Engine moves data asynchronously from the read/write nodes on the host and fpga.
Let me know if you have any questions about any of this.
Sebastian

Passing data from RT host to FPGA through DMA FIFO

Hello,
I am trying to write some data from an RT host to FPGA target using DMA FIFO then process this data and then read them back from the FPGA target to the RT host through another DMA FIFO. I am working on NI PXIe chassis 1062Q, with NI PXIe-8130 embedded RT controller and NI PXIe-7965R FPGA target.
The problem I am facing is that I want to send three different arrays, two of the same size and the third one with different size, and I need the smaller one to be sent to the FPGA first. I tried using flat sequece with two frames in the FPGA VI. In the first frame I read and write the first array in a while loop which is finite (i.e., finite number of iterations). The second frame contains the process of reading and writing the second two arrays (of the same size) in a while loop that can be finite or infinite (according to a control). The problem is that this didn't work. The 2 arrays are displayed on the front panel of the RT host VI and are working fine, however, the array that should have been read in the first sequence doesn't show up on the front panel of the RT host VI. This doesn't make sense because if it is not passed from the host to the fpga and vice versa then the second frame shouldn't have been executed. Note that I am wiring (-1) to the timeout to block the while loop iterations till the passing of each element is complete. Thus the first while loop has 3 iterations only. Could someone help me undersdtand why this happens and how to solve this problem?
I am attaching a picture of both the host and the fpga vi.
Thank you.
Solved!
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Attachments:
RT host vi.png ‏102 KB
FPGA vi.png ‏28 KB

No need to initalize the arrays with values that you will immediately overwrite. Here's what I believe to be equivalent code:
The array outputs should be wired directly to the FPGA FIFO writes. Do not use local variables when you can wire directly.
If you know that you want to transfer the Temp Data Array first, why not make your code do that? Eliminate the sequence structure, and put the functions in the order in which you want them to execute. Use the FPGA reference and error wires to enforce that order. You might consider writing the Temp Data Array, reading it back, then writing the Real and Imag A arrays, to see if that gets you the results you expect. Run the code in simulation (in the project, right-click on the FPGA target and execute on the host with simulated IO) so that you can use execution highlighting and probes to see what is happening. Wire the error wires through and see if you get an error anywhere. Make sure you're not missing something simple like looking at the wrong starting array index.

DMA FIFO number of elements to read mismatch in FPGA and RT

Hi all
I am using myRIO , LV14 to run my application.
Application: I have to continuously acquire data via FPGA and process in RT host once every 2000 samples are collected. I use DMA FIFO (size 8191) to acquire data, use timeout property at the FPGA to eliminate buffer overflow. I had followed cRIOdevguide to implement this part. A snippet of what I have implemented is attached. Whole code runs in SCTL at 50MHz.
Issue: Twice or thrice I encountered with this strange behaviour, that the FPGA FIFO is giving continous timeout and the RT is unable to read the FIFO. The number of elements to write propery in FPGA VI gives 0 showing that FIFO is full and no more can be written, but at the RT, elements remaining is giving 0, hence it is reading 0 (no) elements.
Workaround: I put a case where I will write to FIFO (as per the code) and if the number of elements to write is nonzero. It seems to work fine, as of now.
What confuses me is that my FPGA VI says that FIFO is full (FIFO number of elements to write = 0) and gives a timeout error, but RT VI says that number of elements remaining in FIFO is 0 and hence no data is read. Any idea why it is so? My FPGA and RT VIs continues to run, but with no data being acquired or read.
I saw this behaviour within minutes after running the code. Any idea as to why it is happening? I am trying to reproduce the behaviour and will update if i again encounter with it. Sorry, I cannot post my code here, but i guess the code snippets explain it to some extend.
Thanks
Arya
Edit: Even with the mentioned workaround, the problem persists, now that the FPGA does not write to FIFO at all. And the RT VI is not able to read any elements as it sees 0 elements in the FIFO. The FIFO continues to be in timeout state. So i guess the problem is with the RT side.
Solved!
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Attachments:
cRIOdevguide_FIFOreadwrite.PNG ‏107 KB
FPGA_FIFO_write.PNG ‏41 KB
RT_FIFO_read.PNG ‏39 KB

Hi Nathan
Yes, I could have replaced it with an OR. Regarding my application, I want to acquire data in chunks of 2000 samples. If at all I receive a timeout error, I want to discard that chunk of 2k samples and start all over again. So my logic was like this, I acquire the data, if there is a timeout, the reset is triggered, and the system waits to comeback from reset, and it starts acquiring again. Btw, I tried removing the multiple FIFO reads in RT, but the error is still the same.
I have a small doubt as well, if I do not want to obtain stale data at alI, I would just check if timeout occurs, empty my FIFO and start acquiring data again (no reset button), isnt it? This was my original logic, but I saw that after a while, it stopped acquiring data and timeout led was on. I was thinking that FPGA and RT was simultaneously trying to acquire FIFO which might cause timeout. Somehow, I now feel that, as you have pointed out, my code is overly complicated. I will modify it and update the results. Thank you!
Arya

FPGA Compile error - Actual of formal out port cout cannot be an expression

Details:
ERROR:HDLCompiler:192 - "C:\NIFPGA\jobs\BPO5kq2_O6tyN2U\OC4_Sine_Cosine_LUT_Constant_Amplitude_dash_optimised_vi_c.vhd" Line 1408: Actual of formal out port cout cannot be an expression
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\BPO5kq2_O6tyN2U\OC4_Sine_Cosine_LUT_Constant_Amplitude_dash_optimised_vi_c.vhd" Line 69: Unit <vhdl_labview> ignored due to previous errors.
VHDL file C:\NIFPGA\jobs\BPO5kq2_O6tyN2U\OC4_Sine_Cosine_LUT_Constant_Amplitude_dash_optimised_vi_c.vhd ignored due to errors
-->
The compilation gets to the "Estimated device utilisation" stage but then stops shortly after with a compilation error.
The Line in question (1408) relates to the output of a "Reinterpret FXP" node with the text
cOut => (others => '0'),
in the port map portion of the code. This corresponds to the output of the FXP reinterpret node being directly connected to an indicator in a sub VI whose output is then input directly to a high thoughput multiply node. The code is part of a sinus cosinus LUT I have programmed. It used to compile no problem but I think I know where the problem is. In one instance I only utilise the Sinus output of the algorithm and theoretically, Xilinx can optimise away the Cosinus part. I have two instances of this VI in my code and looking at the one NOT generating errors, the output is associated with a Cosinus indicator.
cOut => s_Cosine_2434,
It would seem that the pathway is essentially optimised away but the Xilinx compiler has a problem with the indicator being present on the sub-VI but the idnicator not being utilised anywhere. As such, the cOut gets set to an invalid value. I assume the immediate proximity of the FXP Reinterpret to the output of the sub-VI is an important aspect of this problem.
I think I know enough now to fix this problem (manually remove the path by duplicating the sub-vi) but this is perhaps a useful feedback for future bugfixes in the FPGA module. This isn't the first time this kind of incorrect code removal has given me problems but it's the first time I've been able to clearly locate the problem.
Shane
Say hello to my little friend.
RFC 2323 FHE-Compliant
Solved!
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I am currently attempting a compile after changing some things.
Just a side question. Is this particular to the Reinterpret node or are other "pink nodes" also affected by this? If I don't connect the output of a high throughput add, will it result in the same behaviour?
PS OK, it seems to be compiling now. I managed to juggle around the nodes a bit in my sub-VI to make sure the "reinterpret" is not the last node before the indicator. It seems to be compiling now. A question which is in my head at this time is: Does the "reinterpret" node prevent anything before it from being optimised away by the Xilinx compiler? Are there other nodes which cannot be removed, even if the outputs are not being used? This would immediately seem to suggest to me that such nodes need to be as close to the source as possible in order to reduce the amount of code which cannot be removed as "dead code" during the Xilinx compile process.
Say hello to my little friend.
RFC 2323 FHE-Compliant

Fpga compile error Port width mismatch

When I try to compile a FPGA vi, the following error occurs.
LabVIEW FPGA: The compilation failed due to a Xilinx error.
Details:
ERROR: [Synth 8-549] port width mismatch for port 'cEIOParameter0Signal': port width = 32, actual width = 24 [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_0000051e_SequenceFrame.vhd:41]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_0000051e_SequenceFrame' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_0000051e_SequenceFrame.vhd:21]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_0000051d_CaseStructureFrame_0002' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_0000051d_CaseStructureFrame_0002.vhd:33]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_0000051a_SequenceFrame' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_0000051a_SequenceFrame.vhd:34]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_00000514_CaseStructureFrame_0001' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_00000514_CaseStructureFrame_0001.vhd:41]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_00000513_CaseStructureFrame_0000' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_00000513_CaseStructureFrame_0000.vhd:50]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_00000510_CaseStructureFrame_0000' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_00000510_CaseStructureFrame_0000.vhd:143]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_00000507_CaseStructureFrame_0001' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_00000507_CaseStructureFrame_0001.vhd:146]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_000004ff_WhileLoop' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_000004ff_WhileLoop.vhd:157]
ERROR: [Synth 8-285] failed synthesizing module 'DM_dash_1575_ModuleResource_vi_colon_Clone19' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/DM_dash_1575_ModuleResource_vi_colon_Clone19.vhd:144]
ERROR: [Synth 8-285] failed synthesizing module 'niFpgaMDKSupportARV_vi_1_colon_Clone18' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/niFpgaMDKSupportARV_vi_1_colon_Clone18.vhd:143]
ERROR: [Synth 8-285] failed synthesizing module 'NiFpgaAG_Manager' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/NiFpgaAG_Manager.vhd:96]
ERROR: [Synth 8-285] failed synthesizing module 'TheWindow' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/TheWindow.vhd:196]
ERROR: [Synth 8-285] failed synthesizing module 'toplevel_gen' [C:/NIFPGA/jobs/Riuys15_TD5ekmx/toplevel_gen.vhd:110]
Finished RTL Elaboration : Time (s): cpu = 00:00:53 ; elapsed = 00:01:04 . Memory (MB): peak = 861.121 ; gain = 715.336
ERROR: [Common 17-39] 'source' failed due to earlier errors.
INFO: [Common 17-83] Releasing license: Synthesis
1738 Infos, 30 Warnings, 2 Critical Warnings and 14 Errors encountered.
synth_design failed
::ERROR: [Common 17-39] 'source' failed due to earlier errors.
while executing
"source -notrace {./.Xil/Vivado-9588-/realtime\toplevel_gen.tcl}"
invoked from within
"synth_design -top "toplevel_gen" -part "xc7k70tfbg676-1" -flatten_hierarchy "full""
(file "C:/NIFPGA/jobs/Riuys15_TD5ekmx/synthesize.tcl" line 25)
invoked from within
"source "C:/NIFPGA/jobs/Riuys15_TD5ekmx/synthesize.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Thu May 07 10:24:37 2015...
I am not sure what the error is all about. Could someone help me?

It's usually better to take a look at where the code failed to compile in the process than trying to read through those logs. In future cases, you'll want to show that information as well.
Depending on your hardware, you might have been able to see the compile happen simply by hitting compile again.

FPGA 2010 Compilation error - TclTasklC:project_028: Unknown property value

Hi, I'm using a cRIO 9075 and a NI 9211 to measure temperature for a project busy with. Everytime I try t compile code I have a compilation error that read as follows:
Compilation failed due to a Xilinx error.
Details:
ERROR: TclTasksC: project_028:Unknown property value "spartan6" specified for "PROP_DevFamily"
Can someone help me on how to resolve this error, I'm using LabVIEW FPGA 2010 and Xilinx 11.5
Regards
Solved!
Go to Solution.

What version of the NI-RIO driver do you have?
Attached is a chart with the different compatibilities of the RIO driver.
NI-RIO and LabVIEW Version Compatibility
http://digital.ni.com/public.nsf/allkb/577CC9A7DCFC73DF8625738400116CC3?OpenDocument
Is this a 64-bit machine? Also, the minimum version of LabVIEW that will work with the 9075 is LabVIEW 2010SP1. You can verify if you have this version by going into Measurement & Austomation Explorer and expanding software. If you do not have LabVIEW 2010SP1, you will need either the platform DVDs for 2010 SP1 or you can download the content from www.NI.com/src.
You will also want to verify that you have the 2010SP1 FPGA module and 2010SP1 RT module.
Also, does this issue occur with all FPGA VIs that you try to compile or only the one that you are currently working on?
You can check by doing two things:
1. Try to compile a blank FPGA VI (i.e. nothing on the block diagram or front panel)
2. Try to compile an FPGA VI from one of the example LabVIEW projects
Please post back if one of these troubleshooting steps resolved your issue or if you're still having problems.
Jordan

Labview 2011 FPGA Compile Error

Hi,
I'm new to FPGA. I want to use Labview 2011 SP1 with the Spartan 3E starter kit from Xilinx (Spartan 3E driver available from NI labview website).
I'm trying to work my way through the examples that came with the driver. I've run into the same compiler error with a number of the examples. The error is attached.
Error 7 occurred at Read from Text File in niFpgaCompileWorker_CheckForErrors.vi->niFpgaCompileWorker_JobComplete.vi->niFpgaCompile_Worker.vi:1
Possible reason(s):
LabVIEW: File not found. The file might have been moved or deleted, or the file path might be incorrectly formatted for the operating system. For example, use \ as path separators on Windows, : on Mac OS X, and / on Linux. Verify that the path is correct using the command prompt or file explorer.
C:\NIFPGA\compilation\Shift_FPGATarget_Shift_87E8371C\Spartan3EStarter.bld
I've checked the registry to ensure that the path to the compiler is correct.
Any assistance would be welcome.
Regards,
James.
Attachments:
Labview2011_FPGA_CompileError.JPG ‏96 KB

Hi,
I don't have any Xilinx tools installed - other than the ones that installed with the Labview FPGA module.
I have attached the compilation logs and output results from my attempt.
I have renamed the extension on the following files from .lvtxt to .txt
BuildResults.txt
CodeGenerationResults.txt
Regards,
James
Attachments:
BuildResults.txt ‏5 KB
XilinxLog.txt ‏42 KB

Data transfer from RT to FPGA using DMA FIFO

Hello all,
My question is "How do you stream data from RT target to FPGA target using DMA FIFOs?"
I would like to control some indicators (or controls) in FPGA vi using controls in the RT vi using DMA FIFO.
I have used four controls in my RT vi, but I get only one indicator out on my FPGA vi. (I would actually like to use some controls on the FPGA target using controls on the RT target)
Is this possible?
Can anyone help me with this?
I have attached my vi s.
Attachments:
fpgatest.vi ‏28 KB
rt_test.vi ‏73 KB

Based purely on your example, I see two options:
1. Do as RavensFan suggests and use Boolean Array To Number to send a single number down to the FPGA. Your FPGA can break up the number easily enough to update the indicators.
2. Just write dirctly to the indicators. I do not see a need for the DMA. Again, based purely on your example.
There are only two ways to tell somebody thanks: Kudos and Marked Solutions
Unofficial Forum Rules and Guidelines

Crio FPGA Compiling error

Hello All,
I've run into a compiling error that has me stumped. I'm using labview 8.5.1, NRIO 2.4.0, and FPGA 8.5.1 on a CRIO-9014 & 9104. When compiling the code attached I get the following error:
Analyzing generic Entity <bushold> in library <work> (Architecture <rtl>).
ERROR:Xst:807 - "C:/NIFPGA85/srvrTmp/LOCALH~1/PLANEV~1/bushold.vhd" line 1541: arguments of 'or' operator must have same lengths.
-->
Total memory usage is 546644 kilobytes
Number of errors   :    1 (   0 filtered)
Number of warnings : 540 (   0 filtered)
Number of infos    :    2 (   0 filtered)
ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...
My best guess is this error has something to do with the metafiles generated by labview before final compilation into the FPGA bitstream. I've tried tweaking the code here and there and haven't found the source of the error yet. I'm going to go through with disable blocks and see where the error lies.
Anyone else run into something like this? I could use some help.
Attachments:
FPGA Code.zip ‏1354 KB

Hi mmalluck,
Clusters of 1D arrays are supported in LabVIEW FPGA. I was able to compile a small VI with code similar to yours - a for loop with four autoindexed tunnels bundled into a cluster.
I am not entirely sure why separating the arrays eliminated that error, but I am glad to hear that your program compiles now.
Jennifer R.
National Instruments
Applications Engineer

FPGA Compile Error due to error in mapping process

Received the following error while trying to compile a FPGA VI on a PC. (Refer to attachment for details). My PC has a fresh installation of English Windows 2000 with sp4. No other software is installed except LabVIEW 8.2 & FPGA Module 8.2 & NI-RIO.
I have checked this KB and confirmed that regional settings are English. But the error still exists. I tried compiling the same VI on my laptop with Windows 2000 sp4 and it was successful. Can someone help me? Thank you very much!
FPGA Compile Error When Compiling LabVIEW FPGA VI
Error found in mapping process, exiting...
Errors found during the mapping phase. Please see map report file for more
details. Output files will not be written.
Design Summary
Number of errors : 17
Number of warnings : 8
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
Message Edited by maimai on 01-08-2007 01:00 AM
Attachments:
FPGA Compile Error.txt ‏8 KB

Hello,
The key will of course be to isolate differences between your machines.
I wonder if the following more specific language setting could be the lingering problem. LabVIEW is a non-unicode program, and there is a language setting in Windows (at least XP) specifically for non-unicode programs. Try the following (or it's Win2K equivalent) if you haven't already:
0. Open "Control Panel"
1. Open the "Regional and Language Options"
2. On the Advanced tab, choose English (United States) from the drop-down menu under the top section "Language for non-Unicode Programs"
- This language setting is different from the setting on the "Regional Options" tab.
Any other differences you can isolate would be potentially insightful - if you have the same software versions installed in the same order on both machines, we may be looking for something a bit subtle, such as the suspected language setting.
Best Regards,
JLS
Best,
JLS
Sixclear

FPGA compilation error 1026 using LV2011SP1

I just upgraded to LabVIEW 2011SP1 and I cannot get a PCI-7831R to compile. In addition to LV2011SP1, I have the following installed:
- FPGA (Version 11.0.1)
- NI-RIO (Version 4.01)
- Xilinx Tools (10.1)
I have a very simple VI that just has a Boolean control on the front panel sending a value to an FPGA I/O on the block diagram. I have created/compiled more complex VI's using LabVIEW 2010 without any issues. My issue with 2011SP1 is that once the intermediate files have been generated, a Code Generation Error screen pops up with Internal Errors. It says
Error 1026 occurred at an unidentified location
Possible Reason(s):
LabVIEW: VI reference is invalid
I'm not sure what VI reference it is referring to. I have tried to compile this just as I have in the past, but to no avail. I have removed previous versions of LabVIEW from my machine and installed/re-installed the LabVIEW software and other modules from the distribution DVD's. It seems as though I always get into trouble when trying to upgrade the NI software.
Is there something that I am missing. I get the same message when trying to compile the examples that are included with the installs. I know that my R-Series card is installed and working properly because I can run sequences via TestStand that call VI's I created using LV2010. Any help would be appreciated!
Attachments:
ErrorWindow.jpg ‏40 KB

Hey Josh,
Thanks for responding. Late friday I added the LabVIEW real time drivers and was able to compile this once earlier this morning with no errors. I then made a small changes (by putting the Boolean control in a while loop) and tried to compile again. Now I keep getting various Xilinx compile errors. Starting to get frustrated since the errors vary slightly every time I try to compile. I will attach a couple of screen shots as well as a zip file that contains the project and VI that I am trying to compile.
Attachments:
tryout.zip ‏26 KB
Screen_Capture02 Apr. 02 12.27.jpg ‏87 KB
Screen_Capture03 Apr. 02 12.30.jpg ‏55 KB

ERROR:HDLParsers:3370 Compile Error when compiling for NI-5640R

I'm trying to get a FFT Core working inside the NI-5640R FPGA. In my latest debugging step, I have received the following error when compiling:
Compiling vhdl file "C:/NIFPGA82/srvrTmp/LOCALH~1/IFBC3E~1/bushold.vhd" in Library work.
Entity <bushold> compiled.
ERROR:HDLParsers:3370 - "C:/NIFPGA82/srvrTmp/LOCALH~1/IFBC3E~1/bushold.vhd" Line 142. Value 0 is not included in the range, 1 to 2147483647, of kConfiguration_ClkMaxWidth.
ERROR:HDLParsers:3370 - "C:/NIFPGA82/srvrTmp/LOCALH~1/IFBC3E~1/bushold.vhd" Line 143. Value 0 is not included in the range, 1 to 2147483647, of kConfiguration_ClkCounterWidth.
Has anybody seen this before? I am including my FPGA VI that is causing this error (FFT (FPGA).vi). I am also including my previous step in debugging the FFT that worked (FFTworking (FPGA).vi).
Attachments:
FFT (FPGA).vi ‏125 KB
FFTworking (FPGA).vi ‏119 KB

Hi,
The main cause of this error message is the large array size. You configured a 16-bit fixed-size array with 4096 element for a total array size of 65536 (16 * 4096). Array uses a lot of FPGA resource and the general recommendation to limit the use and size of array as much as possible on the FPGA VI. This VI will certainly overmap the FPGA resource because of the large array size.
Although this error message is not directly related to the array size, it has however been reported to R&D (#4G3COBJ0) for further investigation. A possible workaround would be to reduce the size of the array or use DMA FIFO to pass the data to the host.
Thanks for the feedback!
Tunde A.
LabVIEW FPGA

FPGA DMA Size Allocation

Hi all,
My application involves grabbing images from a 3-taps, 16-bit camera using FlexRIO. The PXI controller I am using is Windows-based while the FlexRIO module that I have is a PXI-7954 + NI 1483 adapter. The size of the image I am grabbing is 2560 x 2160, U16 and the clock cycle is 100 MHz. I've been trying for over a week and up to today, I still am not able to get the image from the camera as I kept on getting the DMA Write Timeout error. Right now, the DMA size in the FPGA is set at 130k but whenever I tried to increase this further, I get a compilation error. I've tried to have the host program to grab 100k data points from the FPGA DMA at every milisecond but it seems that, I am capped at about 10-15ms. Perhaps, Windows has its own limitation...
Attached is the program that I am using, modified from the LabVIEW shipped example. Please advice, how do move forward from here? or, is it possible to further increase the DMA buffer size up 10x higher than the current limit?
Attachments:
1-Tap 10-Bit Camera with Frame Trigger.zip ‏1684 KB

Hi Shazlan
Apologies for taking so long to reply to you.
You are correct in saying that the latest driver is IMAQ 4.6.4 and this can be downloaded from our website if you have not done so already.
If you have already installed the IMAX 4.6.4 driver, has this managed to resolve your issue?
Also, have you tried to run the compilation again and obtained a report outlining the problems?
As a side note - I have been looking into the possibility of downloading some sort of driver for the Samos camera you are using from Andorra. While National Instruments have not created a driver for this device, Andorra do have a Software Development Kit (SDK) which they say works with LabVIEW. You may find it useful to have this so that you no longer have to write the driver yourself. This may then save resources on the FPGA.
Keep me updated on your progress and I will continue to look into this issue for you.
Regards
Marshall B
Applications Engineer
National Instruments UK & Ireland

HOST to FPGA DMA Transfers

Hi,
We're having trouble using the Host to FPGA DMA feature available in
LabVIEW 8.20 with IFRIO. After starting a compile, we get the following
error message:
An internal software error has occurred.
Please contact National Instruments technical support at ni.com/support
with the following information:
Error -61048 occurred at This target does not support DMA Output (from the host to the target).
Possible reason(s):
LabVIEW FPGA: This target does not support DMA Output (from the host to the target).
Any help would be greatly appreciated.
Thanks.

Hi Manik:
We did not support DMA output on the PCI-5640R when we released NI-5640R 1.0. This is why you are getting the error message that you are seeing.
We plan to add support for DMA output in an upcoming release.
----abhay

Fpga DMA FIFO compilation error

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