Convergenc​e error in mosfet driver NCP5355D circuit, might be bootstrap mistake?

Question

Hi there,
I'm using the Multisim 13.0.1. There's a 8-pin mosfet driver NCP5355D available in the library. I wanted to use it for switching half-bridge MOSFETs, but a simulation error has occured. The report said that 'Transient time point calculation did not converge'.
I've included the circuit with the gate driver, and also the circuit with separate pulsed voltage sources for switching MOSFETs, which could provide a general view of what I intended to achieve with the gate driver.
I also tried to configure the gate driver step by step- I started from the VS, CO, EN, PGND pins side and got no simulation errors then; but when I started connecting the BST and DRN pins, convergence error occurred. So is the convergence error resulting from any mistakes in connecting the BST and DRN pins?
To make it easier, the datasheet of NCP5355D is also attached here, where example application connections are included.
Expecting your insights and thanks in advance!
Solved!
Go to Solution.
Attachments:
cap2-test1_2clk.ms13 ‏183 KB
NCP5355-D.PDF ‏104 KB
cap2-test1_2clk_5355.ms13 ‏172 KB

Answer 1

I do not have Multisim so I cannot see your circuits but have some general observations.
1. MOSFET driver models often use switches and these can lead to convergence problems. This is because the switching action introduces a strong non-linearity into the model.  I wrote my own model using transmission lines for delay and non-linear dependent sources with tanh functions rather than hard switches.
2. If you do not need to model the detailed behavior of the driver, using pulsed sources with rise/fall times as long as possible without changing the behavior of the MOSFETs might be a better choice.
3. There are books written on how to deal with SPICE convergence problems. This is what I found helpful from one of them:
** From Inside Spice by Kielkowski
**   Convergence aids:
**     Select appropriate RELTOL
**     set VNTOL = RELTOL*Vsmall
**     set ABSTOL = RELTOL*Ismall
**     set GMIN = 1/Rp where Rp is parasitic resistance which
***      will have minimal effect when added to circuit.
**     semiconductor models should have non-zero resistances
**        RS (diode), RE, RC (BJT), RD, RS (FET)
**     Raise ITL1=500 (DC OP iterations limit)
**     use .NODESET
**     use source stepping ITL6=500
**  Transient convergence aids
**     Add capacitance to device models:
**        CJO (diode), CJE, CJC, CJS (BJT), CDG, CGS (JFET)
**        CGDO, CGSO, CGBO, CBD, CBS, CJ, CJSW
**     increase ITL4=40
Good luck.
Lynn