Crio 9144 fpga hang

Apparently a cRIO 9144 with custom FPGA code running on it somehow hung / froze. How do I know this? I have a parallel FPGA loop toggling the FPGA LED at a rate of 1 Hz, and the light was just frozen in the ON state. The program on the ethercat master, a cRIO-9074 was still functioning.
Any idea what could cause this?

Hi MarkCG,
So, the application that you are running in the master (9074) is the same running in the expansion chassis and it works fine on the master but hanging on the slave?
Probably you might find interesting the following documents, it explain how you should setup the expansion chassis in order to work with a cRIO controller and also some ways of optimizing your FPGA code.
http://www.ni.com/white-paper/10555/en/ (Ethercat setup)
http://www.ni.com/white-paper/3749/en/ (Parallel Execution and Pipelining)
Regards,
S.Jimenez

Similar Messages

How to use a PID in a CRIO-9102 FPGA

Hello
My name is Francisco, and I'm a student of mechanical engineering in Portugal (FEUP).
I'm working on a project that involves the use of a CRIO-9102 to control a servo hydraulic cylinder. For this purpose I have to implement a PID controller in my FPGA code. Since is not possible to use floating point math how can I do this operation?
Can you pont me to an example that can help me.
Thanks in advanced for any help.
Best regards
Francisco Freitas

Can you tell us a bit more about your requirements for floating point maths?
I write control software for jet engines in custom build microcontrollers with no floating point support. Very often we find something we THINK we might have to use floating point for and discover that we dont!
The most frequently used solution is to establish your maximum and minimum values and instead of scaling your calculations to +/- 1, they are scaled from -32768 to 32767 instead.
Failing that, another option is to use the FPGA as an I/O device and do any floating point work in a Windows host.

Crio multiple fpga vi

Hi,
I have constructed two fpga vi's for cRIO FPGA and tried to run them parallel in a host vi but when I run the host vi then the fpga vi's did not work properly.
I attach the vi's. What is the problem with these codes?
Attachments:
trigger.vi ‏57 KB
host.vi ‏375 KB
fpga1.vi ‏46 KB

Hi,
Unfortunately for you, this thread is correct and you can only have 1 LabVIEW FPGA VI running at a time.
However, here are some tips that may help you out:
It is possible to load different FPGA personalities during run time. Therefore, if you can separate your application into two different applications, you can load them on the FPGA while it is running ( only takes about 1 second to switch the FPGA to another personality)
Instead of putting the multiple FPGA VIs into a top level VI, have you tried to copy the block diagram from one into the other? In other words, combine them into a single VI with multiple parallel loops?
If you are having trouble with space on the FPGA after combining the FPGA block diagrams into one there are many documents online that will help you optimize the FPGA VI. For Example
Combine boolean indicators into a single U32( will save a significant amount of space)
Reduce the usage of arrays on your FPGA VI ( if you have them). There are other methods of storing this data such as a FIFO or the memory on the FPGA
Since you are using the digital only board and if memory serves me right, you can read the port instead of each boolean individually. This would save you some diagram space as well as some FPGA space.
Last but not least, consider contacting a systems integrator to assit with the development of your FPGA VI or the system as a whole. I know of one that does great work with FPGA's: www.viengineering.com .
Mike
V I Engineering

CRIO 9014, FPGA compilation error

i am using cRIO 9014, in that while compiling the code in FPGA i am getting attached error.
please guide me ob that ......
Prashant Soni
LabVIEW Engineer
Solved!
Go to Solution.
Attachments:
errorfpga.PNG ‏42 KB

Hi Prashat,
The error displayed is clear.
Your system time is older than Install time.
Change it to correct time and try it...
Also, if you change your system time (i.e computer time), some softwares will not work. (one more example is Gmail. Try to log into Gmail after settting year to previous year in your system time. It will show SSL error.).

CRIO 9025- FPGA - Not able to access c-series modules integrated with chassis

Hi,
I am using NI cRIO 9025 module. I have conncected the chassis with few cSERIES channels for voltage and current sensing.
When I tried to configure, I am getting the following error
Access denied: This target is running a version of LabVIEW Real-Time that is different than the Real-Time Module software on the host computer. You can verify the version and reinstall the Real-Time software using Measurement & Automation Explorer.
I tried to use Add/Remove option from MAX. But I am not able to update the real time software on cRIO
I am using Labview 12.0 on host computer and on target cRIO9025 - 11.0.1 version real time is installed.
Please kindly help to update the software on target module.
Thanks
Ravi Kishore

NMAYO,
In your project view can you right click on the chassis in the cRIO and make sure that it is set for Scan Mode and not FPGA mode? Also, In the measurement and automation explorer you can check the cRIO and verify that it has Scan Engine Support installed on it. The tutorial below shows how to reformat a cRIO and install software on it, the later steps on software will allow you to check your cRIO.
Reformatting a CompactRIO Real-Time Embedded Controller
Ben Sisney
FlexRIO V&V Engineer
National Instruments

Fpga cRIO NI 9263

Hello guys, I´m new with the cRIO and FPGA, and I really need your help, I´m just wanna do something with cRIO, like setting onde bit in my module NI 9263, just it.
Just set a bit, independent of the out 0,1,2 no matter what port is. I just wanna set a bit for a little test, and then I wanna read this bit with my NI 9205. thank you for everything. and sorry about my english.
please help me. Leonardo
Note: my cRIO model is NI cRIO-9004

obrigado mauro por vc estar dando atenção para este tópico, bom eu estou fazendo um trabalho, com compactRIO modelo 9004 chassis CRIO 9104, e eu tenho os seguintes modulos incluidos nele. NI 9426 NI 9205 NI 9263 NI 9477 NI 9425 NI 9476 NI 9871 respectivamente acoplados ao meu modulo do CRIO, sendo assim eu estou tentando realizar apenas um teste para setar uma saida digital, como por exemplo da NI 9426 ou NI 9476 que são as que tenho aqui. somente isto simplesmente mandar um bit para a saida, e depois poder receber este bit no meu modulo NI 9425 ou NI 9426 e acumular este bit recebido por esta porta em um indicador.
o problema aqui na FATEC de Catanduva é que nenhum professor sabe fazer isto, e estou a semana inteira vendo os tutoriais e tentando fazer este teste,mas nenhum deles faz uma aplicação simples que é a que eu estou precisando.
se você puder me passar seu e-mail eu te mando os prints que tirei de como estao configurados aqui. agradeço desde já a sua ajuda.

FPGA for CAN, DI, AI help getting started

I am a new user to LabView.
I am trying to program the FPGA on a 9144 Ethercat chassis with modules 9423 (Digital input), 9201 (Analog input), 9853 (CAN). 9144 is connected to a cRIO-9024. There are more modules but if I can figure these out, the others should be almost the same.
I have tried to copy the code in the following examples but not all the referenced VI's are on my computer or there is problems with the code that I don't know how to fix
http://zone.ni.com/devzone/cda/tut/p/id/6628
http://zone.ni.com/devzone/cda/epd/p/id/5473
I am able to monitor the digital input and analog input using the real-time VI's, but that is pretty simple.
Normally, I would just pound away at it for a while until I got something that worked, except there are some deadlines that have to be met.
I need to be able to read and write CAN (this is to control a motor). The digital input needs to measure the frequency (Hz) of the incoming signal (count edges). Analog input I would assume would be the easiest as it is just reading a voltage. I realize that the only thing that really needs to run on the FPGA is the CAN. I believe (and hoping) that it is possible to have all the data input come through the FPGA so that the Real-Time VI's only deal with the usable values like Hz and then equate that to RPM for example. I am only looking to extract data at a rate of 1Hz.
If anyone could help me out with some basic code to get me started, I would appreciate it.

This FPGA VI has controls and indicators in it. It can only
run on the FPGA targets that support Interactive Front Panel Communication
(e.g. cRIO-9024) so that the host computer displays the FPGA VI front panel
window and the FPGA target executes the FPGA VI block diagram. Please refer to
LabVIEW Help (FPGA Module) for more information about the Interactive Front
Panel Communication.
However, support of Interactive Front Panel Communications
varies by FPGA target – NI 9144 is one of the targets that doesn’t support it. With
NI 9144, please use User-defined Variables to communicate between the host and
the NI 9144 FPGA target, and then your FPGA VI automatically runs when you
compile and download the FPGA VI to NI 9144 instead of clicking the Run button.
Here is a document about the data transferring between the FPGA and the host. Section User-Defined I/O Variables for Custom FPGA I/O Data describes how to use User-defined Variables.
Transferring Data between the FPGA and the Host (FPGA Module)
Here is more information for your reference:
1. Examples about programming FPGA on NI 9144:
<NI Example Finder> >> Hardware Input and Output >> NI-Industrial Communications >> EtherCAT >> FPGA Fundamentals
2. Help Topics:
<Start
Menu> >> All Programs >> National Instruments >> NI-Industrial Communications
for EtherCAT >> NI-IndCom for
EtherCAT Help >> Programming
the FPGA on NI 9144 Slave Device
Feilian (Vince) Shen

Use of "Open FPGA VI Reference" function --- Build Specification vs VI vs Bitfile

When using the "Open FPGA VI Reference" function in a LV2012 cRIO application, there are 3 options: Build Specification, VI, or Bitfile. What would be the reasons for selecting one over the others? Does it affect the resulting startup.rtexe when the cRIO application is built? I searched through the help and in these forums, but I don't see criteria for selecting one over the others; maybe I missed it.

Hello Chris,
Apologies in advance for a long reply.
The reference method won't change the functionality of your rtexe.exe. They all end up dropping a bitstream, based on a bitfile, onto the cRIO's FPGA.
To a degree, the method used to reference the FPGA code is a matter of taste, but there are situations where one method is better suited than the others.
Reference by VI:
Setting the configuration options to open reference by VI is helpful during development when you are making changes to an FPGA VI often and building/testing using the same spec. When this option is used, a bitfile is selected based on the default build specification for the project. A project may have only one default build specification. You can make any build the default by checking the option under the Source Files category in the build properties. The default build is indicated in the project explorer by the green box around the builds icon.
Reference by Bitfile:
This option references a bitfile directly. Through the configuration window, you can select one specific bitfile to open a reference to (this is not dynamic and does not change unless you physically go make a change to that path). If you're using this method, it helps to give your bitfiles more meaningful names than the ones that are automatically generated by LabVIEW. When you run subsequent compilations off of the same build specification and do not change the bitfile nname or path in the build configuration, the old bitfile is overwritten and replaced with the new one. When you are using this option, it is critical that you keep up with which bitfile is the one you want to be using. There is an option now that will help alleviate any problems referencing by bitfile through the Open FPGA VI Reference function. There is a new VI called Open Dynamic Bitfile Reference. It is typically used when you want to chose a specific bitfile to load depending on something in your host code (a configuration option etc) - but it allows you to dynamically reference a bitfile on the block diagram by path.
Referency by Build Specification:
This option is good for when you want to always use a bitfile that is associated with/compiled with the same build configuration. Say you have two options for top level FPGA VIs in your project (each with its own build spec). Both of these VIs have the same interface (read/write controls, DMA) but they run different algorithms or something. This is nice because you can easily switch your host application between them by picking the build spec associated with the FPGA VI you want to use. In this type of sutation, referencing by VI is no good because you can only have on default build spec.
cheers.
Matthew H.
Applications Engineer
National Instruments

Target types don't show cRIO

Hi Gang,
I'm trying to get a new cRIO Project off the ground for a client. I have LV 2010 and 2012 on my computer. I've got the RT modules in both. I've done one cRIO RT/FPGA project over a year ago.
The cRIO shows "running" in MAX. Some of the modules can be seen in the remote manager application. My gut tells me the cRIO is okay.
When I try to create an RT project in 2012, Compact RIO doesn't show up in the list of target types, so I can't select the cRIO Chassis. Selecting by IP address does put "something" in a project file but no options show up.
I've tried the same thing in LV2010, and all goes as expected, until I try to DL to the RT controller. It returns an error something like: "RT OS unexpected version" probably a newer version.
I think I'm missing some software, or it is not connected to LV2012. NI-RIO 4.0 is installed on my computer. I can see that throught the software tree in MAX.
I didn't expect this part of the project to take even a day to get started, so I'm anxious for help. I'll appreciate all ideas.
Thanks!
Roger
Solved!
Go to Solution.

Hi RogerMont,
You will need NI-RIO 2012:
http://joule.ni.com/nidu/cds/view/p/id/2969/lang/en
DylanC

How to convert double to unsigned long integer for cRIO analog output?

All,
Having issues sending out my arbitrary waveform to my cRIO analog output. My values are doubles and by the time I send them out, they have been converted to U32 values and are all turning out as zeroes. This led me to assume two things: 1) That cRIO analog output can only output integers since the values need to be deployed in the memory first and 2) that I'm missing a step in the conversion process. My values range from 0-8, therefore I don't expect that the simple conversion tool in labview should make everything into zeroes.
Any help?

Since we are using the cRIO's FPGA interface, you really should be doing most of this inside of the FPGA. Use DMA FIFOs to pass your data between your RT and the FPGA (and visa versa).
On your FPGA, you can have a loop that just reads the analog inputs at whatever loop rate you want. You just send the data to the RT using a DMA.
Similarly, use a DMA to send your analog output values to the FPGA. The FPGA can have another loop that reads the DMA and writes the value to the analog output. This should be done in the FPGA since you can have the FPGA send out the values at a given (and deterministic) loop rate.
There are only two ways to tell somebody thanks: Kudos and Marked Solutions
Unofficial Forum Rules and Guidelines

Plusieurs projets qui tournent sur la meme cible FPGA

Bonjour,
Je développe un CRIO en FPGA, et j'ai crée plusieurs projets chacuna un thème différent par exemple: le premier ca sera "verification de la température"pour ceci j'utlise la voie AI0 et le deuxième ca sera "Verification du cycle" pour ceci j'utlise la voie DI0. dans le but de créer des exécutables qui seront appelés par l'utilisateur selon son besoin. La question qui se pose est ce que cela est judicieux est-t-il possible d'avoir plusieurs projets qui tournent sur la meme cible ?!
Je vous remercie par avance pour votre réponse
Cordialement
Nadia
Résolu !
Accéder à la solution.

Oui effectivement comme l'a dis Marc-Junior tu peux utiliser qu'un seul bitfile a la fois.
J'ai lu ton besoin et peut-etre que tu peux voir les choses differements je te propose deux axes de reflexions :
1) Boucle en parallele
Au niveau du FPGA tu as du vrai parallelisme, donc pourquoi pas avoir un VI FPGA qui fait les deux !
C'est a dire une boucle pour la "verification de temperature" et une autre boucle pour la "verification de cycle"
Et vu que tu as du vrai parallelisme si les deux boucles sont indepedantes il y aura aucun probleme, libre a toi apres de recuperer les donnees qui t interresse a un instant T, ou a controler tes boucles avec un control bouleen, en mettant le booleen actif quand tu en as envie.
2) Avoir 2 bitfiles
Si pour une raison X ou Y tu veux VRAIMENT avoir deux bitfiles, certes a un instant T tu peux avoir un seul bitfil qui agit, mais si tu as deux fichier deja compile, il est possible de changer de bitfile quand tu le souhaite.
En gros tu charge le bitfile 1, apres une action utilisatrice tu peux charger le bitfile 2 et ainsi de suite.
Nacer
Nacer M. | Certified LabVIEW Architecte

RT & FPGA Modules – I am missing a fundamental concept

Recently I have been asked to program a compactRIO 9074 and in the midst of researching how to do that, I have become thoroughly confused…
I understand that the RT module is used for precise timing (i.e low jitter) and somehow it interfaces with the host computer (i.e. computer with the VI). I also understand the FPGA module allows you to, and forgive the simplicity, recreate the circuit on the chip, thus allowing virtually true multithreading and really fast speeds. Also, the FPGA interacts with the IO modules/ports.
The thing that I am unclear about is:
When you program the compactRIO 9074, do you select only one module (RT, FPGA) and ignore the other?
-or-
Do you use both modules - the RT module for the embedded hardware and the FPGA module for the FPGA bitstream? If so, how does the embedded hardware talk to the FPGA? Is this something you have to manually program? Any literature/tutorials on this?
-or-
I’ve even read something to the effect- the embedded module gets programmed with the RT module when the cRIO boots up for the first time. If that’s true, then does RT module get used only that only time and all programming thereafter is done with the FPGA module? Is the one-time RT module provided by NI or is this something I would have to create?
I think that I am missing something so fundamentally simple that this whole project is becoming so unnecessarily complicated.
Thanks in advance for the help.
Joe T.

It is a bit complicated, but powerful and flexible. If your needs are simple, NI provides tools (such as the scan engine) so you may not need to get into all the details.
The cRIO is almost a full computer, running a dedicated, real-time operating system (either PharLap ETS or VxWorks, depending on your cRIO). On top of that, there's the LabVIEW runtime. That computer also contains an FPGA, similar to if you bought one of the NI PCI FPGA cards and installed it in your PC.
The FPGA talks to the processor in the cRIO. If you need full control over the FPGA, then you write that code yourself and use DMA FIFOs and front-panel controls to transfer data between the cRIO and FPGA. If you just need access to the IO, you can use the Scan Engine, as previously noted. You also need a way for the cRIO to talk to your computer. Again, you can write code yourself, or use the NI-provided tools such as network shared variables. If you don't need the cRIO to do anything other than act as an expensive data acquisition device, you can link a shared variable to an I/O channel and access it directly from your PC, or share your IO variables over the network. Run a search on the NI site for "network shared variable scan engine" for more information.
You write separate code for the cRIO and the FPGA. You can run your VIs on the cRIO within the LabVIEW development environment and use most of the standard debugging tools, it will just be a bit slower to respond than when the LabVIEW code runs on your PC. When you have a working program, you can build an application and deploy it to the cRIO so that it will run at startup. You can do this as many times as you like. The LabVIEW program on the cRIO may contain an FPGA bitstream embedded in it. Writing code for the FPGA is more complicated - there are limitations, and you must compile the code before you can run it (no interactive debugging unless it's running in simulation).

What is the difference between cRIO and cFP????

Dear All,
We've been working with cFP for a long time and just started implementing cRIO.
what is the basic difference between two of them?
Expecting your prompt reply..
Thanks,
Prashant Soni
LabVIEW Engineer

What do you want to know in addition to what is detailed on the product pages of the two here on NI.com?
One difference: cRIO has FPGA.
LabVIEW Champion . Do more with less code and in less time .

Starting out with cRIO

Hello,
What's the most inexpensive way to start programming for FPGA cRIO based applications? I'm interested in learning to develop for an FPGA and cRIO but can't afford the cRIO, is there an inexpensive way to simulate for these (I think even the realtime drivers may be expensive)
I found this RIO eval kit, but I'm not sure if it's what I need to start learning cRIO/FPGA LabVIEW development?
http://sine.ni.com/nips/cds/view/p/lang/en/nid/205722
much thanks!
Solved!
Go to Solution.

Yes - I agree with GerdW that the myRIO is a great way to get started with cRIO & RT/FPGA programming. It's very easy to set up and use.
I recently used one for a personal project - making a giant version of Tetris! (https://decibel.ni.com/content/docs/DOC-35435)
I can also recommend the eval kit - it comes with a single board RIO an addon board that contains lots of useful things for starting out with RT/FPGA programming (an LCD display, analogue input/outputs that are linked, some push-buttons etc.). I currently have one on my desk at work as we've been doing some stuff recently with LCD displays. They also have onboard CAN (e.g. automotive) so if you're interested in doing anything with that then I don't think you can do that with the myRIO.
If you can't get the myRIO cheaply enough (because you're not a student - but it's worth talking to NI anyway) then the eval kit is a bit more representative of what it's like to use a cRIO and you can get further with it without needing any additional hardware.
Certified LabVIEW Architect, Certified TestStand Developer
NI Days (and A&DF): 2010, 2011, 2013, 2014
NI Week: 2012, 2014
Knowledgeable in all things Giant Tetris and WebSockets

LV 8.5 opens all sub-VI front panels

Hello,
Recently I again saw a strange occurrance that has happened to me about 10-12 times over the past year. Here specifically I am using LV 8.5 with the cRIO and FPGA module. When I was running a new RT VI from the developer environment, (deploying to the cRIO) the result looked something like this:
All the sub-VI front panels are opened, and shown in their reserved or running state.
None of these VIs are set to show front panel when called or opened, but all are sub-VIs of the top level VI within the project. It seems to have replicated a "Find all VIs in memory, within the project" and then "Show front panel" Invoke. The troubling thing is that this is not really repeatable, when I have closed all the VIs and run the VI again, it is fine. I have seen the same behavior in LV 8.2, 8.21 as well as when deploying to cFP-2120 or when on a Host computer.
Has anyone else seen this or are there any ideas of what is going on?
Thanks,
Mello
Message Edited by Mellobuck on 12-11-2007 01:17 PM
Message Edited by Mellobuck on 12-11-2007 01:17 PM
Data Science Automation
CTA, CLA, CPI
SHAZAM!
Attachments:
Multiple Windows.jpg ‏117 KB

Well now that I have seen to image, I recall having seen this myself.
Like you, it was when I was deploying to an RT target and I was not able to recreate this behaviour.
It was either an 8.0 or a 8.2 app.
So all I can do is confirm that you are not alone, but can not offer a solution.
Ben
Ben Rayner
I am currently active on.. MainStream Preppers
Rayner's Ridge is under construction

Crio 9144 fpga hang

Similar Messages

Maybe you are looking for