Crio multiple fpga vi

Hi,
I have constructed two fpga vi's for cRIO FPGA and tried to run them parallel in a host vi but when I run the host vi then the fpga vi's did not work properly.
I attach the vi's. What is the problem with these codes?
Attachments:
trigger.vi ‏57 KB
host.vi ‏375 KB
fpga1.vi ‏46 KB

Hi,
Unfortunately for you, this thread is correct and you can only have 1 LabVIEW FPGA VI running at a time.
However, here are some tips that may help you out:
It is possible to load different FPGA personalities during run time. Therefore, if you can separate your application into two different applications, you can load them on the FPGA while it is running ( only takes about 1 second to switch the FPGA to another personality)
Instead of putting the multiple FPGA VIs into a top level VI, have you tried to copy the block diagram from one into the other? In other words, combine them into a single VI with multiple parallel loops?
If you are having trouble with space on the FPGA after combining the FPGA block diagrams into one there are many documents online that will help you optimize the FPGA VI. For Example
Combine boolean indicators into a single U32( will save a significant amount of space)
Reduce the usage of arrays on your FPGA VI ( if you have them). There are other methods of storing this data such as a FIFO or the memory on the FPGA
Since you are using the digital only board and if memory serves me right, you can read the port instead of each boolean individually. This would save you some diagram space as well as some FPGA space.
Last but not least, consider contacting a systems integrator to assit with the development of your FPGA VI or the system as a whole. I know of one that does great work with FPGA's: www.viengineering.com .
Mike
V I Engineering

Similar Messages

Multiple FPGA targets under one cRIO controller

Hi !
I was reading the cRIO System Configuration Information (CRI) Reference Library article (http://www.ni.com/example/51852/en/) and there Figure 9 shows a cRIO Controller with multiple FPGA targets. How can this be accomplished?
In my case, when I tried to add a 2nd FPGA target, under my cRIO-9076, I get a message that only one can be associated with the controller.
Any ideas ?
Solved!
Go to Solution.

The CRI Library claims support back to LabVIEW 8.5.1, which leads me to believe this screenshot was taken in that version. The RIO Scan Interface/FPGA Scan Engine (RSI) were introduced in LabVIEW 8.6 and NI-RIO 3.0.x. In order to include this support, the notion of a chassis in the LV project was introduced (notice there is no chassis under the controller in the screenshot). To better facilitate RSI and the Scan Engine and provide a more accurate representation of what is actually available in a system, you can only add one chassis per controller. This allows the RSI to load the correct controllers for deployment.
In LV 8.5.1, you can add multiple targets to an integrated controller/FPGA system (like the cRIO-9072) even though there is no way that could happen in real life, so this isn't really that desirable. What you can still do is add multiple FPGA targets (even from cRIO chassis) under the My Computer target in your project. This will still allow you to communicate with the FPGA target, but any VIs will be running on your PC system, not the cRIO controller.
Donovan

Example of Test Bench for multiple FPGA I/O items

Hi,
I'm looking for an example on creating a Test Bench that simulates multiple FPGA I/O digital lines.
I've gone through the Creating Test Benches tutorial but it only uses a single I/O item. Read I/O Item Name.vi is obviously an important part of this but I'm not sure how to structure the VI and assign the name (especially since things seem to get wired up magically for a single IO item).
Any pointers to examples would be greatly appreciated.
Thanks,
Steve
Solved!
Go to Solution.

>>What kind of hardware are you using?
In this case, NI 9401, but we will be expanding to cover several different module types
>>Did you look in the NI Example Finder?
Yes. There are two (in Labview 2011) returned with searching for "testbenches" that are very basic.
>>Which tutorial are you talking about?
http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/test_bench_tutorial/
This shows how to use a Template from the "Execute VI on Development Computer with Simulated I/O" option on the Debugging tab of the FPGA Target Properties. The template covers a single input and it's not clear to me how to simulate more than a single input.
Steve

Is it possible to have a multiple FPGA cRIO system?

I am curios if it's possible to have a single cRIO chassis that can be expanded with additional FPGAs for computations. Meaning, I don't need more I/O but I do have algorithms taking up too much space and need a secondary FPGA to do some parallel processing. Data would be generated in the first FPGA and communicated to the second FPGA where additional processing takes place and then a response/command is sent back to the first FPGA to then be sent out through the I/O.
I saw something "similar" to this in PXI: http://zone.ni.com/reference/en-XX/help/372831C-01/p2pstreamhelp/p2plv_topo_pipelinefpga/
Althought this solution is dependent upon the PXIe bus it has the general feel for what I'd like. However, I need this in cRIO. Is there a solution that I've missed in my browsing of NI.COM?
It would be OK if the solution consumes one of the cRIO chassis slots.
Solved!
Go to Solution.

A cRIO chassis only has 1 FPGA on it. You may be able to get an expansion chassis and pass the data off to it in order to do the processing. For what you are talking about, though, you would likely want to add some DIO so that you can directly communicate with the expansion chassis instead of going through the RT and Scan Engine.
Alternatively, get a cRIO that has a bigger FPGA and/or get with your local NI representative to see if you can get some time with an NI systems engineer who can help you optimize your code to fit on a single FPGA.
There are only two ways to tell somebody thanks: Kudos and Marked Solutions
Unofficial Forum Rules and Guidelines

Multiple fpga vi's with same interface, single RT vi

Hi everybody,
I'm using a crio system to control as experimental setup. In this setup several types of tests can be done and for each, basically the same control is done, but the returned data is different. Therefore i wrote several fpga vi's with the same controls on the interface, and a DMA fifo to transfer the data. I've also written a subvi for my RT system which reads the data from the DMA fifo and transfers it further downstream for analysis. This RT vi has to be rewritten for each FPGA vi as the FPGA vi references are incompatible. How do i make the subvi generic for all these FPGA vi's? The DMA fifo is the same, as is the type and amount of data...
looking forward to your suggestions,
Daniel Lindenaar

Hello Daniel!
I am not sure which FPGA target you are currently using but one method to achieve what you want it to use the Up Cast method. If you use cRIO you have an example called ‘Using the Upcast Function - cRIO.lvproj’ and if you use R-Series look at the example called ‘Using the Upcast Function - R Series.lvproj’. Hope this helps and Merry Christmas!
Regards,
Jimmie Adolph
Systems Engineer Manager, National Instruments Northern Region
Bring Me The Horizon - Sempiternal

How to use a PID in a CRIO-9102 FPGA

Hello
My name is Francisco, and I'm a student of mechanical engineering in Portugal (FEUP).
I'm working on a project that involves the use of a CRIO-9102 to control a servo hydraulic cylinder. For this purpose I have to implement a PID controller in my FPGA code. Since is not possible to use floating point math how can I do this operation?
Can you pont me to an example that can help me.
Thanks in advanced for any help.
Best regards
Francisco Freitas

Can you tell us a bit more about your requirements for floating point maths?
I write control software for jet engines in custom build microcontrollers with no floating point support. Very often we find something we THINK we might have to use floating point for and discover that we dont!
The most frequently used solution is to establish your maximum and minimum values and instead of scaling your calculations to +/- 1, they are scaled from -32768 to 32767 instead.
Failing that, another option is to use the FPGA as an I/O device and do any floating point work in a Windows host.

Best way to synchronize multiple FPGAs

I have multiple PXI-7833R FPGAs and I need all of the AIs to be sampled at the same times (across all FPGAs). As I sample all of the individual AI channels, I buffer the data (write to DMA), scan it and check for a user defined trigger in a different loop. Once I discover this in one channel, I save the data from all FPGAs. In terms of synchronizing the sampling, I had begun, from one FPGA, to send a signal over the PXI trigger line to tell the others to sample, but I assume this does not guarantee synchronization. If I base all of the separate FPGA VIs off of the PXI clock, how do I synchronize the loops to sample at the same clock times?
Thanks
Solved!
Go to Solution.

Hi,
Well, if it's not very timecritical you could pass messages through the host, thats right.
Another way, which is quite hard to implement though, would be to use the other available pxi trigger lines to send messages directly from one FPGA to the other. You would need something like a handshaking, a kind of master who directs which slave is allowed to send, a kind of clock for synchronization and so on.
I cannot give you detailed information, since I never did that by myself, but I know other projects where this works quite good.
Maybe another forums user can give you some better advice.
Thanks,
Christian

CRIO 9014, FPGA compilation error

i am using cRIO 9014, in that while compiling the code in FPGA i am getting attached error.
please guide me ob that ......
Prashant Soni
LabVIEW Engineer
Solved!
Go to Solution.
Attachments:
errorfpga.PNG ‏42 KB

Hi Prashat,
The error displayed is clear.
Your system time is older than Install time.
Change it to correct time and try it...
Also, if you change your system time (i.e computer time), some softwares will not work. (one more example is Gmail. Try to log into Gmail after settting year to previous year in your system time. It will show SSL error.).

High Speed Streaming with Multiple FPGA FIFOs and TDMS Advanced Asynchronous (Data Ref)

I am using an FPGA with adapter card (7962 with 5751) for data acquisition and signal processing. I have adapted the FlexRio example "High Throughput Streaming," which works very well for a transferring data from the FPGA via a single FIFO. This example uses the TDMS Advanced Asynchronous Write (Data Ref). The "High Throughput Streaming" example is similar to "Streaming External Data to a TDMS File (Windows)" but includes more code to prep the FIFO buffer size and TDMS size.
My question is how can I adapt this code to incorporate multiple FIFOs that write data to different channels in the TDMS file? Can I use multiple instances of TDMS Advanced Asynchronous Write (Data Ref) in a single VI for each FIFO Acquire Read Region? If so, how do I insure that the correct data is written to the correct channel in the TDMS file?

Thank you DeppSu for your explanation, I will look into that.
But first, I want to be sure that the FPGA and the Hot general designs are correct, which for the moment I am not sure. So I have included my code.
I tried the Host vi several times, and it seems that it works sometimes and sometimes not, like there are some communication problems between the fpga and the host on the "read acquire region" method which is not executed. I managed to make it work randomly before, but not now. Maybe it is because of the reset that I added?
If someone could check my code and help me, I would really appreciate it since nobody in my workplace has the expertise to do so :-) If you see some obvious mistake, please share with me, I also added some comment boxes in the code with questions.
Delphine
Attachments:
thoughput.zip ‏1261 KB

CRIO 9025- FPGA - Not able to access c-series modules integrated with chassis

Hi,
I am using NI cRIO 9025 module. I have conncected the chassis with few cSERIES channels for voltage and current sensing.
When I tried to configure, I am getting the following error
Access denied: This target is running a version of LabVIEW Real-Time that is different than the Real-Time Module software on the host computer. You can verify the version and reinstall the Real-Time software using Measurement & Automation Explorer.
I tried to use Add/Remove option from MAX. But I am not able to update the real time software on cRIO
I am using Labview 12.0 on host computer and on target cRIO9025 - 11.0.1 version real time is installed.
Please kindly help to update the software on target module.
Thanks
Ravi Kishore

NMAYO,
In your project view can you right click on the chassis in the cRIO and make sure that it is set for Scan Mode and not FPGA mode? Also, In the measurement and automation explorer you can check the cRIO and verify that it has Scan Engine Support installed on it. The tutorial below shows how to reformat a cRIO and install software on it, the later steps on software will allow you to check your cRIO.
Reformatting a CompactRIO Real-Time Embedded Controller
Ben Sisney
FlexRIO V&V Engineer
National Instruments

Crio 9144 fpga hang

Apparently a cRIO 9144 with custom FPGA code running on it somehow hung / froze. How do I know this? I have a parallel FPGA loop toggling the FPGA LED at a rate of 1 Hz, and the light was just frozen in the ON state. The program on the ethercat master, a cRIO-9074 was still functioning.
Any idea what could cause this?

Hi MarkCG,
So, the application that you are running in the master (9074) is the same running in the expansion chassis and it works fine on the master but hanging on the slave?
Probably you might find interesting the following documents, it explain how you should setup the expansion chassis in order to work with a cRIO controller and also some ways of optimizing your FPGA code.
http://www.ni.com/white-paper/10555/en/ (Ethercat setup)
http://www.ni.com/white-paper/3749/en/ (Parallel Execution and Pipelining)
Regards,
S.Jimenez

CRIO multiple Hosts

Hi all,
is it possible to have a crio target running a central VI which exchanges data with host VIs running on different hosts?
Thanks a lot,
Harry
Solved!
Go to Solution.

Hi Chris,
thanks for the reply.. I do not need lossless comms so I guess the shared variables option should be suitable. But what exactly do you mean?
I created a project and then within it a library containing a set of shared variables in my project (under the cRIO target). I then built several host VIs, each sharing some or all of these variables with the cRIO target.. I, obviously, can run host VI (A) from PC (A). However, with host VI (A) running, when I open the project in PC (B) and try to run host VI (B) from it, I get an error message saying
"Access denied: This target is already in use by another project or host computer."
Obviously the way I have defined my shared variables is incorrect, but why??
I have attached a snapshot of my project..
Thanks a lot for your time
Harry
Attachments:
snapshot.JPG ‏128 KB

Fpga cRIO NI 9263

Hello guys, I´m new with the cRIO and FPGA, and I really need your help, I´m just wanna do something with cRIO, like setting onde bit in my module NI 9263, just it.
Just set a bit, independent of the out 0,1,2 no matter what port is. I just wanna set a bit for a little test, and then I wanna read this bit with my NI 9205. thank you for everything. and sorry about my english.
please help me. Leonardo
Note: my cRIO model is NI cRIO-9004

obrigado mauro por vc estar dando atenção para este tópico, bom eu estou fazendo um trabalho, com compactRIO modelo 9004 chassis CRIO 9104, e eu tenho os seguintes modulos incluidos nele. NI 9426 NI 9205 NI 9263 NI 9477 NI 9425 NI 9476 NI 9871 respectivamente acoplados ao meu modulo do CRIO, sendo assim eu estou tentando realizar apenas um teste para setar uma saida digital, como por exemplo da NI 9426 ou NI 9476 que são as que tenho aqui. somente isto simplesmente mandar um bit para a saida, e depois poder receber este bit no meu modulo NI 9425 ou NI 9426 e acumular este bit recebido por esta porta em um indicador.
o problema aqui na FATEC de Catanduva é que nenhum professor sabe fazer isto, e estou a semana inteira vendo os tutoriais e tentando fazer este teste,mas nenhum deles faz uma aplicação simples que é a que eu estou precisando.
se você puder me passar seu e-mail eu te mando os prints que tirei de como estao configurados aqui. agradeço desde já a sua ajuda.

Is an FPGA Host Interface a blocking shared resource?

I'm curious to know if the FPGA Host Interface node is a shared resource. Meaning, if I have a Timed Loop on a LabVIEW Real-Time target (e.g. cRIO) that is reading and writing from the FPGA using the Host Interface. Will the determinism of that loop be adversley affected if I access other signls on the FPGA using the Host Interface in a separate loop (either a Timed loop or a normal while loop).
Said more tersely, is the FPGA Host Interface a shared resource that can cause a priority inversion if called from two seperate loops?
Thanks.
Solved!
Go to Solution.

Hi Southern_Cross
According to our documentation, you should be able to have more than one reference to the FPGA open at the same time ( as long as all the references access the same VI in the FPGA), and use them all in different places in your code from the same target. Since you can only have 1 main VI in the FPGA, accessing the reference of the FPGA behaves more like an I/O than like a non reentrant VI.
Using Multiple FPGA VI References for the Same Target (FPGA Interface)
As long as you are not writing the same variables in both loops (which could cause a race condition) you should be fine.
WenR

Use of "Open FPGA VI Reference" function --- Build Specification vs VI vs Bitfile

When using the "Open FPGA VI Reference" function in a LV2012 cRIO application, there are 3 options: Build Specification, VI, or Bitfile. What would be the reasons for selecting one over the others? Does it affect the resulting startup.rtexe when the cRIO application is built? I searched through the help and in these forums, but I don't see criteria for selecting one over the others; maybe I missed it.

Hello Chris,
Apologies in advance for a long reply.
The reference method won't change the functionality of your rtexe.exe. They all end up dropping a bitstream, based on a bitfile, onto the cRIO's FPGA.
To a degree, the method used to reference the FPGA code is a matter of taste, but there are situations where one method is better suited than the others.
Reference by VI:
Setting the configuration options to open reference by VI is helpful during development when you are making changes to an FPGA VI often and building/testing using the same spec. When this option is used, a bitfile is selected based on the default build specification for the project. A project may have only one default build specification. You can make any build the default by checking the option under the Source Files category in the build properties. The default build is indicated in the project explorer by the green box around the builds icon.
Reference by Bitfile:
This option references a bitfile directly. Through the configuration window, you can select one specific bitfile to open a reference to (this is not dynamic and does not change unless you physically go make a change to that path). If you're using this method, it helps to give your bitfiles more meaningful names than the ones that are automatically generated by LabVIEW. When you run subsequent compilations off of the same build specification and do not change the bitfile nname or path in the build configuration, the old bitfile is overwritten and replaced with the new one. When you are using this option, it is critical that you keep up with which bitfile is the one you want to be using. There is an option now that will help alleviate any problems referencing by bitfile through the Open FPGA VI Reference function. There is a new VI called Open Dynamic Bitfile Reference. It is typically used when you want to chose a specific bitfile to load depending on something in your host code (a configuration option etc) - but it allows you to dynamically reference a bitfile on the block diagram by path.
Referency by Build Specification:
This option is good for when you want to always use a bitfile that is associated with/compiled with the same build configuration. Say you have two options for top level FPGA VIs in your project (each with its own build spec). Both of these VIs have the same interface (read/write controls, DMA) but they run different algorithms or something. This is nice because you can easily switch your host application between them by picking the build spec associated with the FPGA VI you want to use. In this type of sutation, referencing by VI is no good because you can only have on default build spec.
cheers.
Matthew H.
Applications Engineer
National Instruments

Crio multiple fpga vi

Similar Messages

Maybe you are looking for