Detect 0% and 100% PWM Duty Cycles on 660X Card

Hi,
We essentially want to be able to detect 0% (all low) and 100% (all high) duty signals as well as > 0% and < 100% duty.  However, I noticed that when performing buffered pulse width measurement, if either 0% or 100% duty occurs, the previous detected duty is stored.  It seems as if the next edge or level change isn't detected, then the HWSave or SWSave registers store the last successful count.  Is there some flag on a status register for the NI PCI-6602 card that would indicate whether PWM is continuing to be detected?
Thanks,
Jeff S.

Hi Jeff-
You might be able to achieve this operation by setting the Counting_Mode to Synchonous_Source mode.  Check out the descriptions for bits 2:0 of the Gi_Counting_Mode register, as described in the 660x RLP manual page 3-22.  In that mode, you also must set the Gi_Alternate_Sync bit as described on page 3-21.
Without making the change to synchronous counting, you might also be able to glean some useful information about when an error condition has been met by periodically monitoring the Gi_Stale_Data bits, as described on page 3-13.
I haven't tested this, but I wanted to offer a few quick tips to try.  Please give these a try and let me know your results.
Thanks-
Tom W
National Instruments

Similar Messages

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    Solved!
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    Hi Spectre,
    In Multisim, search for the parts base on functionality, there are some PWM models in the database.  Have a look at this knowledge base  if you don't know how to search for parts:
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  • PWM duty cycle update stalls

    Hello
    I want to output a variable pulse width modulated signal via counters. The duty cylce should follow a sine or triangle pattern from 10 to 90 percent.
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    Hello, Frank
    After looking through some documentation, I think that I need RT-HW for what I want.
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    Attachments:
    Unbenannt 1.vi ‏172 KB

  • Measuring PWM duty cycle with Analog Input

    Hello folks,
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    Hi Robert,
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  • How can I measure a 0% or 100% duty cycle signal ?

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    FraB

    Hi,
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    Regards
    DD

  • Dynamic Duty Cycle Change for PWM

    Hello savvy LabView people out there!
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    Attachments:
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    Is something like this for the PWM look like what you had in mind?
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    Attachments:
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  • Bad Duty Cycle readings

    Hello!
     I’m building an application in which I want to measure a duty cycle.  I can control the “Duty Cycle In” and the FCM analyzes the info and sends a signal to the Motor. I want to measure the “Duty Cycle Out” of the motor. (I attached diagram) For this measurement I just connected a wire to the negative side of the motor. To calculate this Duty Cycle I am measuring the period and the pulse width. The program works very good when I have a “Duty Cycle Out” from 1% to 99%, but whenever is 0 or 100% it shows wrong info. I would expect that the pulse width at 0% or 100% is cero, but LabVIEW shows a value (1,1E-5 s) and calculates a Duty Cycle of about 23% which is totally wrong.  Also, if I run the program for the first time and I measure this pulse width with a “Duty Cycle In” of 0%, pulse width is cero., but whenever I change the “Duty Cycle In” to 10% or higher, and then I go back to a “Duty Cycle In” of  0% it shows a value, and calculates a bad Duty Cycle. I don’t know why this only happens when I put higher “Duty Cycles In”, and then I go back to 0%. I measured the signal with an oscilloscope and there is nothing, not even noise! I don’t know how the card gets these lectures.   Do you have any suggestions of what can be wrong?
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    Solved!
    Go to Solution.
    Attachments:
    Diagram.JPG ‏33 KB

    Hi Elmar
    Thanks for the reply. I attached my Code. I am measuring the period with ctr0 and pulse width with ctr1. I divide Pulse Width / Period to obtain the Duty Cycle. To detect 0% and 100% I compare the value of pulse width to zero. I created an additional Digital Input, with this channel I check if the signal is high or low. So if Pulse Width is zero, I read from the Digital Input the level of the signal, and then I know whether is 100% or 0%. My problem is when I have a Duty Cycle of 0 or 100%, the DAQ keeps sending a value for the pulse width, and I cannot apply the method explained before. I think this value should be zero, I don’t know if I am mistaken.    
    Attachments:
    PWM_Measurement.vi ‏61 KB
    PWM_Measurement.JPG ‏151 KB

  • Generate complement​ary digital signals with dead time between each pulse and controlled by duty ratio

    I am to generate  two complementary digital signals using NI 9606 conected by RIO Mezannine Card to NI 9683 (Half Bridge DO).
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    complementary test 2.vi ‏69 KB

    Hi Frank ,
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  • How to decode duty cycle using LabVIEW?

    The duty cycles are output of an accelerometer, which are the input of the DAQcard-DIO-24, but how to decode the duty cycles after acquisition? I knew a timer would be useful, but have no idea about how to perform with labview.
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    --yang
    Message Edited by YangLi on 02-23-2006 05:43 AM
    Message Edited by YangLi on 02-23-2006 05:48 AM

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    National Instruments

  • Analog signal duty cycle incorrect

    I am using an NI PCIe 6535 board to send digital timing signals to a custom PCB.
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    I need the timing signals to run at 833.33333 khz.
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    I am using a DAQmx generate to output the signal to the PCB. I have noticed that the DAQmx gen frequency directly controls the ramps frequency.
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    To get the frequencies that I need. I had to set the"create analog signal" sample rate at 2.778G S/s, the "create analog signal" frequency to 1.2889GHZ, and the DAQmx generate frequency to 1.66666 MHZ. At those numbers, I get the timing signals to output at 833.333KHZ and the second bit of the ramp at 416.6666HZ (for the ramp I upped it to 13 bit and I don't use bit 0, as it outputs at 833KHZ).
    However at these settings all of my timing signals have the same phase, and the same duty cycle, even though I have them set differently.
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    Attachments:
    timing signal 1.JPG ‏44 KB
    timing signal 2.JPG ‏47 KB
    daqmx gen.JPG ‏55 KB

    Hi David,
    We found that there seems to be a weird divider between the sampling rate of the analog signal module, the analog signal sample rate, and the f daqmx gen.
    After various tests we made a chart of what we observed. Fsignal and sample rate are values set in the "create analog signal" module, Fdaqmxgen is set in the "DAQmx generate" module. We used a "create anaolg signal" module to create the square wave, then convert analog to digital convert the square wave to digital.
    We have "repeated signal" and "N periods" checked.
    Fsignal
    Fdaqmxgen
    Sample rate
    Frequency   measured on the scope
    1GHZ
    10MHZ
    100G s/s
    100KHz
    100MHZ
    10MHZ
    100G s/s
    10KHZ
    1GHZ
    1MHZ
    100G s/s
    10KHZ
    10GHZ
    10MHZ
    100G s/s
    1MHZ
    100GHZ
    10MHZ
    100G s/s
    10MHZ
    100GHZ
    10MHZ
    100G s/s
    5MHZ
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    How do I set the compression to false?
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  • Problem to measure 0% and 100% duty cycle of a PWM.

    Hi,
    I am using counters of USB-6341 to measure duty cycle of PWM just by following the example 'Meas Duty Cycle-Buffered-Finite.vi'. It works almost all the time. However, when the duty cycle of a input pwm is 0 or 100%, the DAQ can't read anything, in another word, it can't measure 0 or 100% duty cycle.
    How to modify that?
    Thank you very much :-)
    Nan

    That's the thing about PWMs, you never really know if the PWM is 0% or 100%.
    Let's say we have a 50% duty cycle, at 1/2Hz.  So low for 1 second, high for one second right?  What if we run at 1/20Hz, so low for 10 seconds high for 10 seconds.  Or is this a 0% duty cycle for 10 seconds, and a 100% for 10 seconds?
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    So I would recommend taking your duty cycle like you normally are, and then at the same time watch the digital signal for however long you want, if the digital line does not change state, then output 0% if it is low and 100% if it is high and ignore what ever duty cycle you read.  But if the digital line does change state, then use the read duty cycle as the actual value.
    Unofficial Forum Rules and Guidelines - Hooovahh - LabVIEW Overlord
    If 10 out of 10 experts in any field say something is bad, you should probably take their opinion seriously.

  • I want to store the data form the PWM and the value of the changing duty cycle into a file simultaneously and continually

    i want to store the data form the PWM and the value of the changing duty cycle into a file simultaneously and continually but having problem.Please can anyone help out.
    Attachments:
    data.vi ‏60 KB

    Hello,
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  • How can I vary a PWM´s duty cycle inside a while loop?

    Hi,
    I'm using the "Generate Pulse Train.vi" to generate pwm signals in counters 0 and 1 in order to drive a DC motor both ways.
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    So, how can I vary a PWM´s duty cycle inside a while loop?
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    Guilherme
    Attachments:
    controleValvula.vi ‏332 KB

    Here's some code I threw together a while back to change a duty cycle on the fly. It generates a fixed 5KHz or 25KHz frequency depending on laser selection, then allows duty cycle to be changed continously. Maybe you can use the premise of it for your application.
    ~~~~~~~~~~~~~~~~~~~~~~~~~~
    "It’s the questions that drive us.”
    ~~~~~~~~~~~~~~~~~~~~~~~~~~
    Attachments:
    Pulse_Width_Modulator.llb ‏197 KB

  • How to generate a pwm whose duty cycle has to be varied depending on the frequency of the input trigger??

    Sir/madam,
    I am quite new to the Labview FPGA module. 
    I am currently working on an application where i have to generate a pwm to control the ON time duration . The pwm ON time depends on the frequency of an input signal.I want to retrieve the ON time value from a lookup table which contain the duty cycle values for the pwm at different frequencies of the input.This input also has to work as a trigger. The input is pulsed and the trigger has to generate the pwm at every rising edge. I am using a PCI 7831R-  RIO series. I am urgently in need of some help and i have hardly a  couple of weeks before i meet the deadline.
    I am trying hard to learn the basics from the shipping examples but not able to quite make my vi work. 
    Kindly lend a helping hand and i would be very grateful to anybody who can help. Thanks a lot in advance.
    Do ask in case of any clarifications required. I  think i have explained my problem quite well. 

    Hello Manu,
    You can refer 
    Developing a PWM Interface using LabVIEW FPGA or PWM Output with LabVIEW FPGA
    How this helps.
    Best Regards, 
    Hardik Asawa
    AE
    National Instruments  
    Message Edited by Hardik Asawa on 05-05-2010 12:46 AM

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