EM simulation problem

Hi,
I have been trying to solve this EM simulation problem in the attached project (from a customer) but with no luck. I have tried changing the interpolation/passivity options, switching to APLAC simulations, different AXIEM settings with/without AFS, #sim points, DC frequency in the EXTRACT block etc but the simulation just wouldn't complete without error. The consistent error is 'Vector fitting failure' for which I could find no help. I am sure there is something I'm missing here, would someone be kind enough to take a quick look and tell me how to go about solving this problem ?
Thank you!
Attachments:
LNA_grndpr_finfab1_toAWR.zip ‏94 KB

Hi,
I am looking into this issue right now. The ports are set up wrong on your extracted document, so I am trying to figure out a way to set them up correctly. I will get back to you once I find out more.
Thanks,
Ideen

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Attachments:
if490.txt ‏7 KB

I have Mutlisim 10 and under the simulation tab there is VHDL Simulation. Apparently in mine it is only a demo, but you can create VHDL components. I tried compiling your file, but it tells me that it is too large for the demo. It also says this " Better yet, purchase the fully function simulator by calling your local Electronics Workbench reseller".
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http://ni.kittmaster.com
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Attachments:
multisim.PNG ‏39 KB

Hase,
I checked the spice model for the rectifier that you are using and got it to work. I attached the picture that shows which variable you have to modify, it was set to 100V... that is why you would get that fuzzy thing going on... according to the datasheet it should work up to 1000V right?...
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Nestor
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Attachments:
rectifier.JPG ‏23 KB

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Java Card 2.2 Class File Converter (version 1.3)
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Hi Joseph,
I guess what you mean is there is something wrong to the command below:
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I tried the command below, but got another error:
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Java Card 2.2 Workstation Development Environment (version 0.18).
Copyright 2002 Sun Microsystems, Inc. All rights reserved.
jcwde is listening for T=0 Apdu's on TCP/IP port 90,250.
java.lang.IllegalArgumentException: Port value out of range: 90250
Exception on TCP/IP socket port # : 90250
jcwde terminating on receipt of SimulationException. See previous messages for
cause.
com.sun.javacard.jcwde.SimulationException
*********************************************************Sorry, I am very new in java card, so might need a little bit more explanation if you don't mind.
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Attachments:
Block DIagram.jpg ‏146 KB
Current-Matrix.png ‏27 KB
Dummy-Matrix.png ‏12 KB

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Hello, I have following problem. There is a module with two inputs and one output. Is input clock signals and a long (relative to frequency) asynchronous strobe. In identifying the strobe (0 to 1), the modules must be put to the output pulse of a long period of frequency.
I have implemented this module as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pulse_gen is
port (
CLK : in std_logic := '0';
STROBE : in std_logic := '0';
PULSE : out std_logic := '0'
end entity pulse_gen; -- pulse_gen
architecture Behavioral of pulse_gen is
begin
generation : process( CLK )
variable strt_pulse : std_logic := '0';
variable prev_strobe : std_logic := '0';
begin
if (rising_edge(CLK)) then
--STROBE 0-to-1 catching part
if (prev_strobe = '0' and STROBE = '1') then
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strt_pulse := '1';
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if (prev_strobe = '1' and STROBE = '0') then
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--STROBE 0-to-1 catching part end
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strt_pulse := '0';
PULSE <= '1';
else
PULSE <= '0';
end if ;
end if ;
end process ; -- generation
end architecture ; -- Behavioral
and I am using it for this test:
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
ENTITY tv_sync_gen_tb IS
END ;
ARCHITECTURE tv_sync_gen_tb_arch OF tv_sync_gen_tb IS
SIGNAL CLK : STD_LOGIC := '0' ;
SIGNAL STROBE : STD_LOGIC := '0' ;
SIGNAL PULSE : STD_LOGIC := '0' ;
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PORT (
CLK : in STD_LOGIC ;
STROBE : in STD_LOGIC ;
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CLK <= not CLK after 5 ns;
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STROBE <= '1' after 55 ns,
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PORT MAP (
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END ;
the result was the following timing diagram:
But if I implement modules little different then getting another temporary diagram.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pulse_gen is
port (
CLK : in std_logic := '0';
STROBE : in std_logic := '0';
PULSE : out std_logic := '0'
end entity pulse_gen; -- pulse_gen
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signal strobe_interconnection : std_logic := '0';
begin
strobe_intcon:
strobe_interconnection <= STROBE;
generation : process( CLK )
variable strt_pulse : std_logic := '0';
variable prev_strobe : std_logic := '0';
begin
if (rising_edge(CLK)) then
--STROBE 0-to-1 catching part
if (prev_strobe = '0' and strobe_interconnection = '1') then
prev_strobe := '1';
strt_pulse := '1';
end if;
if (prev_strobe = '1' and strobe_interconnection = '0') then
prev_strobe := '0';
end if;
--STROBE 0-to-1 catching part end
--PULSE driver
if (strt_pulse = '1') then
strt_pulse := '0';
PULSE <= '1';
else
PULSE <= '0';
end if ;
end if ;
end process ; -- generation
end architecture ; -- Behavioral
PS .: What literature I should read to avoid similar errors?

Clearly you have a race condition. Your first case changes the strobe and clock lines at exactly the same time including delta time. That's why it doesn't delay the pulse like you see in the second case. If strobe is a synchronous input, it should be changed only 1 delta delay (or more) after the rising clock edge in the test bench. If strobe is an asynchronous input, then your code will not work correctly in hardware because the prev_strobe variable is being compared to an asynchronous input signal, and therefore the time when one is high and the other low can become infinitesimally small when the input signal changes just before the clock edge.

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SUB R1 R1 R1
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I might have some ideas but I'm a little unclear on where you are stuck. So if I have totally gone off the rails here just bear with me.
In pseudo code let's say I have two lists (or arrays). One is a list of instructions and the second is a list of "registers" or buckets to hold values.
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1) Set register 1 to 5
2) Set register 2 to -3
3) Set register 3 to 4
4) Multiply register 1 by 2 and store it in register 4
5) Add register 4 and 2 and store in 5
6) Subtract register 3 from from 5 and store in 6
7) Print 6
So the register list looks like this.
1) Set register 1 to 5
5 0 0 0 0 0 0
2) Set register 2 to -3
5 -3 0 0 0 0
3) Set register 3 to 4
5 -3 4 0 0 0
4) Multiply register 1 by 2 and store it in register 4
5 -3 4 10 0 0
5) Add register 4 and 2 and store in 5
5 -3 4 10 7 0
6) Subtract register 3 from from 5 and store in 6
5 -3 4 10 7 3
7) Print 6
3
I dunno.

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