FPGA I/o node

Hi, I was wondering if the following FPGA I/o node acquires Mod1/AI0, Mod1/AI1, Mod1/AI2, and Mod1/AI3 simultaneously.
I mean I don't know if they are at the same time or not.
Solved!
Go to Solution.

I checked out the specifications of the module NI 9234, as in the following figure.
As shown, for this module, all the four channels are sampled simultaneously.
Now I'm sure!
I think for every module, we should check out the specifications to make sure.

Similar Messages

[FPGA] Loop rate very slow: Do FPGA I/O nodes in parallel loops block each other?

Hi,
I am using cRIO-9075. Mod1 is NI 9263, Mod2 is NI 9227, Mod3 is 9215.
Please see my VI attached or the given screenshot.
The FPGA code is based on the "NI CompactRIO Waveform Reference Library" (it's the lower loop).
The upper loop was added by me and is writing a waveform from blockmemory to the NI 9263 module (Mod 1).
The data sampled in the lower loop is running at 1 kHz. The control "AO Update Period" for the upper loop has a value of (for example) 10 (=uS).
The problem is, that this loop is running much much slower than it should. Once I disable the FPGA I/O node in the lower loop (as done in the attachments), it's running as fast as it should.
It seems to me, that the FPGA I/O nodes are blocking each other. I tried to figure it out by reading through serveral NI documents, but until now I have no idea how to solve that.
Can you give me some advices? Some general tipps about the VI?
Thanks!
Attachments:
FPGA Loop Rate.PNG ‏72 KB
FPGA Main.vi ‏251 KB

Hi, thanks so far.
Originally the control was inside the loop. Then I tried if it makes a difference if it's outside.
Ok, i really seems to be that default value of "100000" for "AO Update Period".
Starting the VI directly woks like expected. Having "AO Update period" inside the loop makes it possible to control it as it's running.
But, please see the attachment. When starting the FPGA through RT and setting the appropiate value, it does not seem to work. The oscilloscope show's the same behavior like "AO Update Period" was 100000.
But when reading the value of "AO Update Period" afterwards (while the FPGA is running), it shows the expected value of "10".
Having changed the default value to 10 works so far, but I am not able to changed it (see attachment).
So the problem is: Why is "Read/Write control" not working here? Why is still the default value used?
Attachments:
FPGA Loop Rate 2.PNG ‏5 KB

Fpga i/o node error - input is not configured

I'm trying to run through the sbRIO eval kit tutorial, and am getting the following errors from HD44780 FPGA.lvlib:
The FPGA I/O In parameter on the FPGA I/O Node is wired to an input that is not configured. Select an I/O item from the control or constant. You also can configure the input by right-clicking the control or constant and selecting FPGA I/O Category from the shortcut menu.
I'm really at a loss since I'm just learning how to utilize FPGAs in LabVIEW (2011 SP1), and was getting similar errors on my own.
I'm using the "NI LCD Module Driver, 1.1.0.11" driver installed by the VI Package Manager.
Any help will be greatly appreciated.
-B-
Attachments:
HD44880_FPGA_vi_errors.png ‏60 KB
OpenRun LCD Screen.zip ‏192 KB

Hey Scottso,
Right click the FPGA target in your project and select new-> FPGA I/O. You should see the mezzanine card in a tree structure. Expand it and all your IO shoudl be available underneath. Press the arrow to add the channel to your New FPGA I/O Listbox then press OK. It should then put the IO into your project to be used. You can then drag the I/O from your project and drop it on your block diagram. Another option is to click on the node you have shown and choose "Add New FPGA I/O" or if you already have the IO in your project you can click the node and choose "Select FPGA I/O"
CLA, LabVIEW Versions 2010-2013

Pass value to FPGA I/O node in FPGA.vi from Host.vi

How do you pass a different value to the FPGA.vi I/O node from the Host.vi?? In the FPGA I made the I/O node a "control" but when I try to use Read Write control in my host none of the I/O show up in the drop down selection. All my booleansare there. See screen capture.
Thanks..
Solved!
Go to Solution.
Attachments:
fpga I_O.jpg ‏124 KB
fpga I_O.jpg ‏124 KB

nathand wrote:
Ben wrote:
You have to recompile the FPGA code and then relink to the new version for the control to show up. The "wire" has the infor on the control and if you are using an wire that did not know about the new control...
By the way, if you're using a reference to an FPGA VI (and not a bitfile), there's no need to recompile to pick up changes to the controls on the front panel of the FPGA VI. However, IO node references do not propagate to the host VI. The reason for FPGA IO node controls is for subVIs within an FPGA design, not for host-to-FPGA communication.
Unfortunately, this really is a bit misleading. When I was first learning FPGA, I got caught up in this when I tried to use a config file to set the IO nodes up like you would for DAQmx. I understand why it isn't really possible, I just wish there was some way it would notify the programmer of this. I even took the FPGA class from NI and I don't think they ever mentioned this was not possible.
I do like the idea of routing the signals using a case structure though, that's a good idea. The only issue is if you want to have all channels available without a recomile, you have to acquire from them all even when unused, just in case the user decides to use them down the road.
CLA, LabVIEW Versions 2010-2013

Using an FPGA Read Wirte Node from inside a OO Class

I'm trying to develop an object orientated program for a RIO.
In the broadest of terms I'm just try to use one of my VI's to change the status of a control on the FPGA. Even with putting the FPGA reference in to the encoder typedef I'm unable to select the control as the VI doesn't know which FPGA it's referenceing.
Is there a way to do something like this?

I've just done as suggested here: http://forums.ni.com/t5/LabVIEW/Typedef-FPGA-VI-Reference-Does-Not-Retain-Interface-Definition/td-p/...
And that appears to be working.

FPGA with HDL node

I am using a PCI-7831R. I have a VI that is basically putting out data into a board that we aare devoloping. I also have a HDL node as another VI that looks at frames sent out from another board and picks out words from certain locations in the frames. I want to know if I can run this HDL node VI along with the other VI. Thanks
Bibin

Hello Bibin,
You should be able to run both VIs at the same time if you place them in parallel inside a bigger Main VI. So, both VIs will be running as subVIs.
The only restriction would be if they were talking to the same IO channels.
Hope this helps.
Ricardo S.
National Instruments

Controlling fpga digital output node from realtime boolean

I have a system where I want to turn on / off a digital output running on the FPGA.
Once I set the boolean on my realtime side (which turns on the FPGA output), I see the output turn on the CRIO, but it flickers on and off. (not latching?). I just want the FPGA to stay on as long as the output is turned on, on the realtime side. I cant change the mechanical action of the switch due to limitations on FPGA / RT according to labview ( I get an error at compile)
Any suggestions on how to correct this?
Solved!
Go to Solution.

I have simplified my program to something very basic to replicate the problem.
The digital output D0 switches on and off everytime the realtime loop cycles through.
If I run just the FPGA seperate and turn on the digital output control D0 it stays on solid. (until I turn it off again)
What am I doing wrong?
Attachments:
FPGA_RT_TEST.zip ‏144 KB

How do you create the FPGA I/O Start Node shown in the NI 9233 Getting Started FPGA VI

The fourth frame of the sequence structure in the NI 9233 Getting Started (FPGA) VI (from examples, browse by task, Toolkits>>FPGA>>cRIO>>AI>>Modules>>9233) shows an FPGA I/O node with a Start Terminal. Can someone tell me how to generate the Start Terminal in an FPGA I/O Node?

The Start and Stop terminals of the 9233 module are handled the same as digital lines from DI and DO modules. To access them in the diagram you first need to add them as digital I/O channels in the project.
Once you have added the 9233 module to the project, select to add I/O channels to your project. Instead of adding analog channels, go to the Digital Line Output section (see attached image) and select the Start and Stop signals from the 9233.
Back in your diagram you can then add a FPGA I/O node and select these signals.
Message Edited by Christian L on 12-11-2006 04:41 PM
Christian Loew, CLA
Principal Systems Engineer, National Instruments
Please tip your answer providers with kudos.
Any attached Code is provided As Is. It has not been tested or validated as a product, for use in a deployed application or system,
or for use in hazardous environments. You assume all risks for use of the Code and use of the Code is subject
to the Sample Code License Terms which can be found at: http://ni.com/samplecodelicense
Attachments:
9233iochannelconfig.JPG ‏38 KB

FPGA LabVIEW 2011 Compilation Crash - I/O Node

When I try to compile this FPGA LabVIEW code then LabVIEW crash every during" Generating Intermediate Files"
It don't like these "FPGA I/O in" variables in FPGA I/O Node.
Constants "POT_net_1_x" are same standard DIOs.
Hardware: PXI-7841R
Solved!
Go to Solution.

Hi JCC,
Glad you got it to compile, it may have been that LabVIEW got a corrupted file somewhere in the project that was causing an issue and by rewriting the code you bypassed this problem.
If the further problems relate to a problem with FPGA compilation then you could post them here, otherwise it is probably best to create a new thread with a title that relates to that problem, that way other people will know what the thread is about and it they know the answers or have suggestions they will help.
Kind regards,
James W
Controls Systems Engineer
STFC

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

Detecting C Series Module Fault through I/O Variable Node

Hello LabVIEW Users.
My name is Eisuke Ono, An Application Engineer at NI Japan.
One of our customer is requesting a function.
The function is to retrieve information of module fault from C Series I/O variable Node (Scan Interface).
I know that we can get the information of module fault through FPGA I/O node, but not through Scan Inteface mode.
The customer's application is embedded condition monitoring system. It runs 24/7.
So it is very convenient if he get information of module fault C Series I/O variable Node Error Output.
I agree his opinion.
What do you think?
Bestr regards.
Eisuke Ono

RT
FPGA
The goal is to detect Module Fault (Other than Communication Error) through IOV or FPGA node.
If it is already implemented, I would delete this thread.
Best!

FPGA project - custom cRIO module driver development

Hi!
I'm developing the driver for my custom cRIO module. The module has 4 analog input channels.
After analog-to-digital conversion I need to transmit the digital data via the cRIO bus.
I placed an FPGA I/O node on my block diagram (see the attached image), but I can only read if the pin's state is HIGH or LOW, not the value of the ADC.
How can read the value of the conversion?
Thanks for the help,
Levi
Attachments:
driver proj.jpg ‏192 KB

Hi!
After some research I managed to create the connection between my custom cRIO module and LabView.
The complete solution (with LabView 2011):
- add line 'cRIO_FavoriteBrand=generic' to the LabView.INI file
- launch LabView
- creating an empty project and select FPGA as execution target, click GO
- select 'CompactRIO Reconfigurable Embedded System' as project type, click next
- the next step is the detection of the chassis/ modules, followed by the creation of the new FPGA project
- adding the custom module: right-click on FPGA Target -> New -> C Series Modules -> New Target or Device -> C series Module -> OK
- Enter name, select as module type 'generic', enter location
Hope it will help someone someday.
Levi

How can i know that my FPGA VI logic is placed correctly on the FPGA???

Helloo,
I am very new to LABVIEW and using LV8.0 version
I am using cRIO-9002, cRIO-9101 chassis, NI-9401 in slot1 of the chassis. I have written some simple VI which will take True or False as a input and based on that output will come as 12 or 3 respectively. I am writing this output at DIO[7:4] of NI-9401. My VI is running successfully , generating intermediate files and BIT file also. In the Front panel i am able to see correct output also. But when i see the output at the output pins of NI-9401, nothing was coming. I am attaching my file. In this i have used FPGA I/O node to write output on that pins of NI-9401. My Q is
1. Can i expect output pins of NI-9401??
2 . Is there anything is to be done or write anything interface VIs..etc are to be done to get the outputs.
3. My way of procedure is complete or not??
Help me in this issue plz.
Reagrds,
Ravi Kumar.
Attachments:
simpleAIAO.vi ‏38 KB

Hello Eli S,
But still i am not getting.
I am seeing voltage level at DIO pins of NI9401 as 0V only.
I observed that in MAX
Cofiguration >> my system >> software >> NI-VISA version is 4.1
and
Cofiguration >> remote system >> software >> NI-VISA version is 3.4.1
will it be a problem?? I am setting initial line direction as a output port in the project explorer NI9401 module and also set the line direction as a output in front panel.
Is there any chance of problem in hardware?? like connection between the FPGA(chassis cRIO9101) and NI9401??
how can i check that my hardware is working perfeclty??
I am thinking that the only way is what i am doing right now...like writing digital data to lines...will be a simple experiment to check my hardware.
Sorry, i may be wasting your time, but if I overcome this problem, i can start my application on cRIO which is bigger in logic.
Thank you very much.
Regards,
Ravi Kumar.
Attachments:
Digital Line Output.vi ‏269 KB

How can I set the timebase in the FPGA API for the NI 9853 CAN module?

Hallo,
is there anybody familiar with cRIO, especially the NI CAN 9853 Modul?
When starting communication with a CAN Bus you can get a receiving CAN Frames from the FPGA I/O Node with a timestamp.
How can I set this timebase in the CAN Controller, because the CAN communication starts every time with the same timebase.
Compared to the CAN API on a PC the timebase for the communication is set when the Open Frame API VI is used?
From that time the CAN Contoller assume the timebase from the PC.
Whats about the FPGA API?
Martin

Hallo Dirk,
thanks you
for your answerer regarding my question.
The last
question belongs to my intention, to get absolute Timestamps from the NI 9853
CAN interface. As you said it always starts from zero when starting the
application.
For my application
I would like to get a timestamp with the local time I start the CAN communication
and every CAN Frame should be logged with the Timestamp it is actually send on
the CAN BUS.
How can I achieve
it?
My first
thoughts were to add up the timestamp for every CAN Frame counted from zero to
an absolute Timestamp when starting communication. But I have got some wrong values.
Maybe I did something wrong using the high and low part of the Timestamps I got
from the CAN API.
Do you have
a suggestion for me?
MartinW

Fpga code generation error after updating from 8.5.0 to 8.5.1

Hi All,
I have a FPGA-VI which was compiled in LV 8.5.0 without errors. After I updated to 8.5.1 the Code Generation stops, telling me the clock domain is not supported for write FPGA I/O node (see attachment). Also I attached a picture of a simplified FPGA-VI which brings up the same error.
I use a PXI-7833R connected to a cRIO-9151 R Series Expansion Chassis with a NI-9421 modul (8-ch DI, 24V) installed in it.
My original FPGA-Code has a theoretical maximum of 22MHz, so I can't change the clock domain to 40MHz.
Do you have any suggestion how to get the VI compiled?
Uli
Solved!
Go to Solution.
Attachments:
ErrorMessage1.jpg ‏30 KB
FPGA-VI1.jpg ‏17 KB

Hi Ruhmann, hi Basset Hound,
thank you for your reply and giving me a better insight in things.
I started my VI with 40MHz clock domain. The Vi got bigger, some more logic here and some more code there. Finaly the compiler couldn't satisfy the timing any more. Instead of optimising the code, I reduced the clock domain.
Until your post I didn't realise I use CompactRIO I/O. Is There a difference to (let me call it) "direct R-Series I/O"?
I need the Expansion Chassis (Connector 1), the 9421 (8-ch DI) and 94?? (8-ch DO) to connect 24V logic to the FPGA. Additionally I have two SCB-68 (Connector 2+3) for 5V logic (DI, DO, A/B linear position measurement, pulse generation) and some analog input. All code in 1 VI, but distributed in 3 loops.
To change the clock domain back to 40MHz, I have to optimise my code . Well, the code is sloppy , so optimising is OK .
To tell the hole story:
After updating to 8.5.1, my first contact to NI was by phone. The engineer asked for the Code, the project and the hardware.
It took a while for me to put the information in an email. Meanwhile engineer the found a paper with the solution I
mentioned in my second post and send it to me, before looking at my code. The paper said someting about "tightend timing constraints",
"safe communication" and "multiple DMA target to host transfer". Not exactly what I was doing, but I reinstalled
RIO 2.3.1 and ... compile successful.
@ Basset:
The simple VI (picture) in my first post reproducese the issue exactly.
I'm not at work any more, so I can't provide the full code or the SRQ# until tuesday (holiday on monday ).
FYI I'm located in Germany, so I called the german NI support.
Uli

FPGA I/o node

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