Fpga IO module clock with TRIG

Hi,
I'm working with the "IO module clock 0" at 100MHz. My problem is when I'm compiling, I get Error Place905. I found out that it's because I'm using a PXI trigger inside the timed loop. Is there a solution to use triggers with this clock? 
I joined the error log and the VI.
I must use that clock.
I'm programming 16 NI PXIE-7962R FLEXRIO FPGA in a PXIE-1075 EXPRESS CHASSIS.
Thank you
Attachments:
Error905.png ‏163 KB
VI_trig.png ‏13 KB

Thanks Jordan for the update,
In fact, we can now use the IOModuleClock0/IOModuleClock1 with PXI triggers and timed loop but we still have compilation errors when using IOModuleClock0/IOModuleClock0... not a real problem now but here is a screenshot of the compiation problem..
If yu have any clue...
Thanks a lot and have a nice day !!
Nicolas
Attachments:
error 905.png ‏369 KB

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