GTX transceiver wizard set CPLLREFCLK="101" in property/xci generate and stay for dcp ooc?

VC707 - transceivers wizard 3.5 ...
How do I with GTX transceiver wizard set CPLLREFCLK="101" so I can select my gt0_gtsouthrefclk0_in (which I'm in QUAD 113 so this is from QUAD114 correct)?
I currently have to open ..._multi_gt.vhd and the _funcsim.vhd/.v files and edit the:
SIM_CPLLREFCLK_SEL => "101",
cpllrefclksel_in => "101",
from the default "001"
The attached is my current .xci. --
I'm not sure about wizard page Line Rate,RefClk the "Transceiver Selection" I have my GTX X1Y2 from QUAD0 o ngui =QUAD113 for real set to get clk from QUAD1 per gui=QUAD114 for real REFCLK0_Q1 to my CPLL ... not sure what this does but closest thing to selecting the southrefclk0 I guess...?
I also include shared logic in example design since I think I don't want to step on my prior pcs_pma core that used include shared logic but still uses same QUAD113 - ch1 for phy.
I tried to find in .xci or report_property something to set the CPLL sel but don't see it..
currently I will set my .xci to global and delete my .dcp which will then just build from source right..
PS- when I change funcsim CPLLSEL signals it doesn't seem to simulate for them, just the "001"...?
THANKS!

Thanks, I've been looking at those diagrams for some time and just don't understand clearly. May you please point me the right direction for my application:
VC707 board, using QUAD113 the SGMII on GTXE_CHANNEL_X1Y! is already working using it's MGTREFCLK0 SGMII_CLK and now I want to get the GTXE2_CHANNEL_X1Y2 SFP+ transceiver in the same QUAD113 working using the Si5324 MGTREFCLK0 from QUAD114 as it's CPLL input.
I can't get CPLL lock. Since this Si5324 clk is from QUAD114 MGTREFCLK0 above I believed I should tie my design Si5324 clk input pin signals through an IBUFDS_GTE2 to the GTSOUTHREFCLK0 pin of my gtwizard GTXE2_CHANNEL for my SFP+ transciever. However in the design view it appears the Si5324 clk pin into QUAD 114 is mapping to GTSOUTHREFCLK1 in the diagram so I tried that as well. I've also tried to just tie it to GTREFCLK0 and/or 1, change to appropriate CPLLREFCLKSEL, and also to tie it to all the advanced clks...
Where shoudl I tie the Si5324 clk input signal -- what should my CPLLREFCLKSEL be set to.
If I understand your response it sounds like since I'm never changing clks to the SFP transceiver and only tieing one, I just leave CPLLREFCLKSEL = '001' and tie it to the GTREFCLK0?
THANKS!

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