How can I make a control inside a loop in a subVI change value when the calling VI's control changes?

Question

Hi.
I think this is a pretty basic LV question, but I have not been able to find a good solution.
I am attaching VIs that show the problem I am having, but obviously, the real application is a lot complicated, which forces me to try to do it this way.
The issue is: I have a subVI with a Boolean control inside a loop.  When the control is true I want some action to take place.  When the subVI is run on its own, it works fine, acting properly when I set the boolean control to true via the LV FPGA interface from the host.  However, when I use it as a subVI, in which the top-level VI calls several instances of the subVI, I have the Boolean controls in the top level VI.  What is happening is that the false Boolean value with which the top-level VI starts is passed into the subVIs, and not updated, even though the control is inside the loop.
Can any one suggest a good solution?
Thanks,
AlejandroZ
Attachments:
CallingVI.vi ‏7 KB
subVI.vi ‏8 KB

Answer 1

Hi.
I know the example I posted might seem silly, but it was just to illustrate the problem I am having.  In reality this is the application:
I have some LV FPGA code which uses a few FPGA IO to implement a serial link to communicate with a device.  Most of the time we are getting data from the device, so the serial link is used to send a read command, read in the data and put it into a FIFO.  However, I also wanted the VI to support sending data to the device, so I added an array control to put the data you want to send, and a boolean control to tell it you want to send it.
Since sending and receiving data are done using the same FPGA IO, they cannot be independent operations, because they would garble each other. Therefore, in the subVI I have a loop in which I first read data if there is any to read, then check the boolean write control to see if there is data to write.
As I mentioned, this works perfectly for talking to a single device.  However, we run into the issue of this topic when trying to replicate this for several devices.
One easy solution is to not have the loop in the subVI, and have it in the calling VI (I am favoring this simple solution right now).  The only reason why I have not done this yet, is that the subVI has more than one loop, so I am going to have to create several subVIs.  I just posted to see if there was an even simpler solution...
There have been some other possibly good solutions proposed here, though I am not sure if they work in LV FPGA.
Thanks for all your responses.
AlejandroZ