How can we let logic in the implemetation process not to squeeze together?

Question

Hi xilinx expert:
           There are three clk domain in my project . green, yellow and red clk domain. i don't understand why they are all place in the lower part of the device. All logic is squeeze together in the lower part, and the upper part is empty. The design did not meet timing requirements.
            How can i get the yellow and green clk domain logic layout to the upper part of the device?

Answer 1

We had the same problem.  PBlocks are your friend.  You can chose which logic you want to move and where you want to place it, including having overlapping blocks.  We do things like:
set N 11;
set PB [create_pblock Cust_$N]
add_cells_to_pblock $PB [get_cells -hier -filter [list NAME =~ *\[$N\].mCustPort]]
resize_pblock $PB -add {SLICE_X158Y488:SLICE_X165Y498}
resize_pblock $PB -add {DSP48_X13Y196:DSP48_X14Y199}
set PB [create_pblock Cust_$N\_RX]
add_cells_to_pblock $PB [get_cells -hier -filter [list NAME =~ *\[$N\]*mDecode*]]
add_cells_to_pblock $PB [get_cells -hier -filter [list NAME =~ *\[$N\]*mFifoRx*]]
resize_pblock $PB -add {SLICE_X170Y488:SLICE_X191Y498}
resize_pblock $PB -add {DSP48_X15Y196:DSP48_X16Y199}
resize_pblock $PB -add {RAMB36_X11Y98:RAMB36_X11Y99}
The results look like this:
It is hard to see why you cannot use this to solve your problems.