How to generate a chirp(linear FM) signal using dds theory in LabVIEW FPGA.

how to generate a chirp(linear FM) signal using dds theory in LabVIEW FPGA.
attachment:a sine signal using dds theory. Hope to get some help. Thanks!
Attachments:
FPGA DDS SineGen IP.vi ‏42 KB

you need to increment the "accumulator increment" during the duration of the chirp.  the "accumulator increment" controls the frequency of the DDS cycle.  by increasing it's value, you are increasing the frequency.  the math for increment values follows the same math as determining the frequency to increment value.
Stu McFarlane
Viewpoint Systems, Inc.

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