How to get saturation function in system generator

Hi,
I use system generator and try to achieve the saturation function by using Xilinx Libary.
For example, how could i get a function which is similar to the block "Saturation" in normal simulink library.
The back ground is that i have a PWM signal in my FPGA model. Now i want to cut the negtive value. Or change all the negative value to zero.
Thank you.

The gateway in blocks have saturation option for saturation at the ports. For signals internal to the sysgen design, you can use the Convert block which also allows saturation option.
 

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