How to refactor ActionScript code into Utility or Helper Classes ?

Hello
My application is growing in size. Many of my components are now 1000+ lines of code, most of which is ActionScript functions.
What is the best way to refactor this into classes? Are there any tutorials explaining something like this?
I'd like to do something like "myComponent1Util" and "myComponent2Util" respectively, to handle common functions. I notice I have a lot of functions that could be refactored into smaller functional code.
Anybody have any tips or advice before I journey down that road? It would be appreciated.
Thanks!

There is no general rule of thumb. Most probably your classes are overloaded
with responsibilities. You can try to read Martin Fowler's refactoring as a
starting point. Examples are in Java and C# but you'll get the big picture.
C

Similar Messages

How to restructure this code into separate classes?

I have C# code that initializes a force feedback joystick and plays an effect file(vibrates the joystick). I have turn the console application into library
code to make a dll so that I can use it in LabVIEW.
Right now all the code is written under one class, so went I put the dll in LabVIEW I can only select that one class. labVIEW guy told me that I need to
restructure my C# code into separate classes. Each class that I want to access from LabVIEW needs to marked as public. Then I can instantiate that class in LabVIEW using a constructor, and call methods and set properties of that class using invoke nodes and
property nodes.
How can I do this correctly? I tried changing some of them into classes but doesn't work. Can you guys take a look at the code to see if it is even possible
to break the code into separate classes? Also, if it is possible can you guide me, suggest some reading/video, etc.
Thank you
using System;
using System.Drawing;
using System.Collections;
using System.Windows.Forms;
using Microsoft.DirectX.DirectInput;
namespace JoystickProject
/// <summary>
/// Summary description for Form1.
/// </summary>
public class Form1 : System.Windows.Forms.Form
private System.Windows.Forms.Label label1;
/// <summary>
/// Required designer variable.
/// </summary>
private System.ComponentModel.Container components = null;
private Device device = null;
private bool running = true;
private ArrayList effectList = new ArrayList();
private string joyState = "";
public bool InitializeInput()
// Create our joystick device
foreach(DeviceInstance di in Manager.GetDevices(DeviceClass.GameControl,
EnumDevicesFlags.AttachedOnly | EnumDevicesFlags.ForceFeeback))
// Pick the first attached joystick we see
device = new Device(di.InstanceGuid);
break;
if (device == null) // We couldn't find a joystick
return false;
device.SetDataFormat(DeviceDataFormat.Joystick);
device.SetCooperativeLevel(this, CooperativeLevelFlags.Exclusive | CooperativeLevelFlags.Background);
device.Properties.AxisModeAbsolute = true;
device.Properties.AutoCenter = false;
device.Acquire();
// Enumerate any axes
foreach(DeviceObjectInstance doi in device.Objects)
if ((doi.ObjectId & (int)DeviceObjectTypeFlags.Axis) != 0)
// We found an axis, set the range to a max of 10,000
device.Properties.SetRange(ParameterHow.ById,
doi.ObjectId, new InputRange(-5000, 5000));
// Load our feedback file
EffectList effects = null;
effects = device.GetEffects(@"C:\MyEffectFile.ffe",
FileEffectsFlags.ModifyIfNeeded);
foreach(FileEffect fe in effects)
EffectObject myEffect = new EffectObject(fe.EffectGuid, fe.EffectStruct,
device);
myEffect.Download();
effectList.Add(myEffect);
while(running)
UpdateInputState();
Application.DoEvents();
return true;
public void PlayEffects()
// See if our effects are playing.
foreach(EffectObject myEffect in effectList)
//if (button0pressed == true)
//MessageBox.Show("Button Pressed.");
// myEffect.Start(1, EffectStartFlags.NoDownload);
if (!myEffect.EffectStatus.Playing)
// If not, play them
myEffect.Start(1, EffectStartFlags.NoDownload);
//button0pressed = true;
protected override void OnClosed(EventArgs e)
running = false;
private void UpdateInputState()
PlayEffects();
// Check the joystick state
JoystickState state = device.CurrentJoystickState;
device.Poll();
joyState = "Using JoystickState: \r\n";
joyState += device.Properties.ProductName;
joyState += "\n";
joyState += device.ForceFeedbackState;
joyState += "\n";
joyState += state.ToString();
byte[] buttons = state.GetButtons();
for(int i = 0; i < buttons.Length; i++)
joyState += string.Format("Button {0} {1}\r\n", i, buttons[i] != 0 ? "Pressed" : "Not Pressed");
label1.Text = joyState;
//if(buttons[0] != 0)
//button0pressed = true;
public Form1()
// Required for Windows Form Designer support
InitializeComponent();
// TODO: Add any constructor code after InitializeComponent call
/// <summary>
/// Clean up any resources being used.
/// </summary>
protected override void Dispose( bool disposing )
if( disposing )
if (components != null)
components.Dispose();
base.Dispose( disposing );
#region Windows Form Designer generated code
/// <summary>
/// Required method for Designer support - do not modify
/// the contents of this method with the code editor.
/// </summary>
public void InitializeComponent()
this.label1 = new System.Windows.Forms.Label();
this.SuspendLayout();
// label1
this.label1.BackColor = System.Drawing.SystemColors.ActiveCaptionText;
this.label1.Location = new System.Drawing.Point(8, 8);
this.label1.Name = "label1";
this.label1.Size = new System.Drawing.Size(272, 488);
this.label1.TabIndex = 0;
// Form1
this.AutoScaleBaseSize = new System.Drawing.Size(5, 13);
this.BackColor = System.Drawing.SystemColors.ControlText;
this.ClientSize = new System.Drawing.Size(288, 502);
this.Controls.AddRange(new System.Windows.Forms.Control[] {
this.label1});
this.Name = "Form1";
this.Text = "Joystick Stuff";
this.ResumeLayout(false);
#endregion
/// <summary>
/// The main entry point for the application.
/// </summary>
[STAThread]
static void Main()
using (Form1 frm = new Form1())
frm.Show();
if (!frm.InitializeInput())
MessageBox.Show("Couldn't find a joystick.");

Imho he means the following.
Your class has performs two tasks:
Controlling the joystick.
Managing the joystick with a form.
So I would recommend, that you separate the WinForm from the joystick code. E.g.
namespace JoystickCtlLib
public class JoystickControl
private Device device = null;
private bool running = true;
private ArrayList effectList = new ArrayList();
private string joyState = "";
public string State { get { return this.joyState; } }
public bool InitializeInput() { return true; }
public void PlayEffects() { }
private void UpdateInputState() { }
So that your joystick class does not reference or uses any winform or button.
btw, there is a thing which is more important than that: Your polling the device in the main thread of your application. This will block your main application. Imho this should be a job for a thread like background worker.

How to separate "random" code into their own place. (with source code)

Hi, i can't seem to figure out how use random to separate the letters and how you would select the individual code from the menu and display it. I know a major part of the code is missing, so any help will be greatly appreciated.
Here are my instructions.
thanks
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2.     Create a randomly generated password from the character sets selected by the user.
3.     Check the strength of three passwords of different length from each menu option with the password checker. Tabulate the strength of your 12 passwords (see instructions below).
4.     Re-read the Strong Passwords: How to Create and Use Them article and write a short paragraph giving your opinion about the effectiveness of randomly generated passwords vs. memorable passwords (see instructions below).
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I also have to select from the menu that I types in the code.
* Write a description of class Password here.
* @author (your name)
* @version (a version number or a date)
import java.util.Scanner;
import java.util.Random;
public class Password
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        Random randomGenerator = new Random();
        int randomInt = randomGenerator.nextInt(26);
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        System.out.println("*   [1] Lowercase Letters                                   *");
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I suggest you start by creating a function which takes all the parameters for generating a password and returns a randomly generated password. Then create a method for each of the other key functions such as checking the password strength.

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Hi,
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Abu_ramla

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A catch,
try {
// Some code
} catch (Exception e) {
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/Andrew

(AS3) How to divide my code into classes/package

Anyone familiar with this? I have already tried dividing
among classes and it is not working.
I have created the following code that pulls data from an
external xml file into a datagrid. I have been trying to figure out
how to get it to function using classes and/or packages. I'd like
to separate the functionality into separate classes for each of the
following:
1) A class for loading the XML file(s) (there will likely be
more datagrids and more xml files)
2) A class for "drawing" the datagrid based on the xml
.... others you can think of??
I have attached the code in question.
Thanks,
Mark

Classes in AS3 need to be in packages now, e.g.:
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in class look up targets
package {
// import statements go here
// needs to be public for access outside of package
directory
public class NewXMLClass {
// again public makes it accessible to other classes
public function NewXMLClass() {}
// inlcude your methods here
use an import statement to use it in other classes e.g.
import NewXMLClass;
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How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

In general, how do I put code into a loop?

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VARIABLE enum NUMBER;
EXEC :enum := 7566;
-- my procedure. Cannot change code here.
-- Prints out a formatted name and job, given an empno stored in :enum
SELECT ename || ' (' || job || ')' AS "myrow"
FROM scott.emp
WHERE empno = :enum;
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something like this:
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CURSOR e_cur IS
SELECT empno
FROM scott.emp
WHERE job="MANAGER';
END;
BEGIN
FOR r_cur IN e_cur LOOP
:enum = r_cur.empno
-- my procedure. Cannot change code here.
-- Prints out a formatted name and job, given an empno stored in :enum
SELECT ename || ' (' || job || ')' AS "myrow"
FROM scott.emp
WHERE empno = :enum;
-- end of my procedure
END LOOP;
END;
{code}
of course, this code does not work, and I don't know what else to try.
Thanks in advance for any help!
Skip

Oh boy, do I owe you guys an apology. Absolutely no excuse, but I screwed up big time yesterday. I am working on a couple of projects and got some wires crossed. I would like to start over. Forget everything I asked yesterday. I wouldn't be surprised if no one answered, but I could still use some help. I am embarrassed because I am usually pretty good at these things, and again, I humbly apologize.
Still with me? Here we go:
I have a SQL script that is quite long. It has 25 select statements, 4 unions, 7 minus'es, lots of joins, sub-queries, etc. The script expects two bind variables to be set before running. The code was written to execute once (like a report). But the code does exactly what I need, but I need to run it on a much larger set. So I would like to wrap it in a loop. Now, I am pretty good at other programming languages (I know, hard to believe given yesterday's exchange). If I have some java code that I want to wrap in a FOR-NEXT loop, often all I need to do is put one line at the top of the code and one line at the bottom. Then I make sure the variables that need t be updated through each iteration are properly updated. Bada-bing, bada-boom, it's done.
It doesn't seem as easy here. I know that I will have to convert my SQL script to PL/SQL. But I am wrestling with the DECLAREs, BEGINs and LOOPs, and changes to the existing code to ensure the bind variables are updated each iteration. I have tried all of what I thought would be the simple solutions as I described with my java example above, but it has not worked. So, as my subject line indicates, I was wondering if there was a general methodology to LOOP-ifying existing code. I know this is a pretty nebulous question, and I probably blew it yesterday, but I really do need some help. Even if it is "read this and that website/book/etc". That's really it. sigh All that stuff yesterday about "unmodifiable code"--forget about that. I should never have said that. Anything goes.
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How to add new codes into SAP Query/Infoset

Hi Experts,
First time working with SAP Query.
I need to enhance an existing Query to add a new field into a report. I have added new tables into this Infoset and joined my new tables with existing tables and able to extract the new fields out on the report. But here are my problems:
Example of original output:
X88888 500000
X99999 400000
Example of new output after adding my 2 new tables to get 1 new field to output:
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X88888 50000 01/25/2009      <--- for X88888 customer, I want only this record w/ latest date to be output
X88888 50000 01/22/2009
X99999 40000 03/09/2009
X99999 40000 04/18/2009
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Where/How i can add the code to control this logic so that only 1 record per customer with the highest date can be output. I looked at the query program and it looks very confusing and hard to understand.
Please advise,
Thanks,
Sam

Hi Sam,
Instead on adding new table/tables , better way to use Direct Read from your single table.
Please read the below steps to suffice your requirement.
Assumption: Let your original table be A and second table is B.
                        Tables A and B are having field X1 and X respectively, using these fields, they can be joined.
                         You want field date1 of table B.
Infoset Changes:
1. Go to SQ02 (Enter Infoset name, click on Change button)
2. Create an extra field E_date of type date (Sy-datum), by clicking on 'Extras' (F5) button.
3. Select that field in one of the field group of your Infoset.
4. Click on Code Icon (Shift+F8) displayed on application bar, you will be getting lists events in 'Code section'.
5. In Data Section , declare an internal table like below code (here pseudo code)
data: begin of itab_date occurs 0,
                   date1 like B-date1,
                   end of itab_date.
6. In Recod processing Event write the following code.
CLEAR itab_date.
CLEAR E_date.
SELECT date1 FROM B into table itab_date                           " Retrieving date field from table B
WHERE X = A-X1.
Sort itab_date by itab_date-date1 DESCENDING.                 "Sort internal table B in decendind order on date1
READ TABLE itab_date index 1.                                            "Read first record of interanal table
E_date = itab_date-date1                                                      "Assigning top most date of internal table into field E_date.
7. Generate the Infoset
Query changes
1.Go To SQ01 (in a new session),
2.Give your Query name, click on change button, and select that field group in which you have added extra field.
3.Select extra field.
4.Go to basic list to select that field in your O/p list.
5.Click on Test button, and see if you are getting desired result.
Please let me know if you need further details.
Regards,
Dinesh

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1* select * from v$version
SQL> /
BANNER
Oracle Database 10g Enterprise Edition Release 10.2.0.1.0 - Prod
PL/SQL Release 10.2.0.1.0 - Production
CORE 10.2.0.1.0 Production
TNS for 32-bit Windows: Version 10.2.0.1.0 - Production
NLSRTL Version 10.2.0.1.0 - Production
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I use method (File>new>file.) create a html under my project . but when I swith web dynpro perspective, can't found the html file under my current project ?
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