I believe I have a timing issue...
Greetings:
Ok, I'm writing an application that has a main class I.E. Class1, Class1 creates Class2 which as it is loaded populates a combo list box during Class2.run(); by using a public static method entitled getTransactionCodes();
Class1 creates a private static instance of Class2.
Class2.cbxTransCode has a mouse listener associated with it. If the user right clicks the cbxTransCode an instance of Class3 (a popup menu) is created and the user can click a number of options in this case the Add.
Class3 creates yet another instance of Class4... a dialogue which prompts the user to enter a new code into the database. Upon successful validation an instance of Class5... DataControl is created.
The newly entered and validated code is stored to the db with a PrepairedStatement as suggested to me last week.
Great, the new code is entered into the db. Now I call Class1.getClass2().getTransCode();
The first line of the getTransCode method clears the combo box and then proceeds to populate the widget as it had when class2 was first created.
Great... however the new code doesn't appear... I then close Class2 and reopen it and low and behold the new code is in the list... I have varified that the combo does get cleared out and repopulated with a loop...
So, where am I going wrong... should I have some sort of Wait or Sleep method evoke. Keep in mind that I'm coming from the VB way of doing things.
Jim
I've resolved my own issue.... wonderful thing that
new contraption, I believe they call it the
Internet.
Anyhow, I used "Thread.sleep(100);" to allow my code
to catch up.
JimI can only echo what jverd said. Think about what will happen when the sleep time is not as long as the process time it's waiting on. Based on your code you're waiting 1/10th of one second (100 ms). What will happen when it takes 2/100th of one second to finish what it's waiting on? Not pretty.
A better plan and very simple to implement would be to wait .1 seconds just like you are, but when it wakes up check for a flag that will be tripped when the other process finishes. if it's tripped go on your way. If it isn't, loop around and sleep again.
There are sexier ways to do it but this will work, with one caveat. You are introducing a wait state into your application and creating delay for your users. Also if the process you're waiting for doesn't trip the flag you're waiting for ever.
PS.
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Timing issues in implemented design
Hello everyone,
I have been reading in these forums for a long time now, but have never posted. Possibly because I have never had such a design-specific issue that was above my knowledge...I wish my problem was more "friendly" for a first post.
Anywho, my problem is as follows: I've been working on a design for a few months now and everything was working fine up until recently (apart from logic errors of course that I would run into and fix here and there). I recently integrated a module that I did not design myself. My behavioral simulations work fine and all of my previous functionality seems to be working as well when the design is implemented. However, the functionality based on the "foreign" module has introduced problems.
What I am using: Spartan 6-XC6SLX16 and therefore ISE
Here are some of the functional symptoms I have recorded so far:
- The functionality always produces the same output after the design is implemented and uploaded
- The functionality can differ if I change something (no matter how small or where) in the design itself
- The same applies for changing constraints
- After some implementations+uploading the functionality works correctly, and in other cases it fails by either producing erroneous results or just "getting" stuck (i.e. one of my FSMs)
- The critical path w.r.t. my system clock is in the module that seems to be the source of the problems
This leads me to believe that there is some timing-related issue. The only timing related constraint I have used is for my system clock period. The timing report does not show any errors regarding this constraint.
My guess so far would be that I have an unconstrained path problem, possibly in combination with insufficient account for system and input jitter, as the design does take up around 40-50% of FPGA. The problem is that I have no experience in tracking such an issue down, so I could definitely use some pointers in the right direction.
Things I have tried:
- Basic logic debugging of the input-output behavior of the problematic functionality using chipscope
- Post-PAR simulation of the module that includes "foreign" components: Works fine with a 100MHz constraint
- Increasing the frequency constraint for the entire design from 100 to 120 MHz but that was just out of lack for better ideas, it did not help.
- Looking at the unconstrained paths that the timing analysis can provide. I was hoping to find something related to the component that seems to be causing the problems, but no luck. Mainly just entries related to all of the ring oscillators that I am using, which it seems to be interpreting as a clock domain crossing case. These, however, have nothing to do with the problematic portion of the design.
I have a few questions at this point:
-Can one problem lead to a totally uncontrollable landslide of other seemingly independent problems?
-Also, how do I make sure that I get ALL of the unconstrained paths and not just a subset?
-Could it even be an unconstrained path issue if nothing in the report indicates that there is an unconstrained path in the problematic region?
I hope I have described my problem thoroughly enough for you to make some educated assumptions about what could be going wrong. I'm interested in learning what typically causes such problems. I am aware of synchronizing between clock domains, or the de-assertions of asynchronous resets, the standard problems...but I missed something critical here and I don't want it to happen again. Perhaps somebody has a pointer for me where I could do a little more digging?
I will set up a timing simulation of the entire design, but as this is a rather lengthy process it will be some time until I get some results.
Cheers,
ShibbyHello,
Thank you for the quick replies so far.
austin wrote:
So, my questions to you are:
Did you review the entire (verbose) timing report?
What is your smallest positive slack number?
What is your system jitter? Your clofck source jitter?
How well is the device bypassed on the board you are using (is it one of ours, or one from our distributors)?
- Yes, I went over the entire verbose timing report that DIDN't cover unconstrained paths. However, when I did have the timing analyzer output unconstrained paths as well, there were a lot of timing errors. I assume this is due to the fact that unconstrained = period requirement of 0 and the slack is therefore always negative? I had a look at these and none of them really indicate a problem to me.
- The smallest positive slack in the case of the standard verbose timing report was 0.304ns.
- The system jitter is (the default?...I did not specify it in my UCF) 0.070ns. The other jitter values (TIJ and DJ) are both set to zero. So the resulting clock uncertainty is very small...possibly too small.
- The board is a Nexys 3 from Digilent. I assume they know their stuff when it comes to capacitive bypassing of ICs. How would this play a role? If I've understood correctly then this is correlated to the system jitter. Bypassing problems would lead to larger/more frequent voltage dips (especially for larger designs) and therefore a clock that exhibits more/larger uncertainty (i.e. jitter)?
I think my lack of knowledge in correctly constraining larger designs might be causing the problems here. But perhaps also not, so just to be sure, I want to ask the following (possibly stupid) questions:
- Instead of increasing parameters related to jitter of a certain clock, wouldn't increasing the period constraint of that clock have the same effect? As I wrote, increasing for example the system clock constraint to 120MHz rather than 100MHz showed no improvement of the problem...I'm not sure what this tells me...if anything at all.
- I do have another clock domain and I do synchronize signals (there is nothing big going on, mainly just handshaking) between the two domains. What could the effect be if I removed the period constraint for one of the clocks apart from possible timing problems in that clock domain?
- The ring oscillators that I have clock certain FFs if oscillators enabled, however I do not know their exact frequencies. Would it suffice to just use a known upper bound?
The latter two questions concern parts of the design that habe been there for a long time and have no functional connection to what was added that seems to be causing the problem, though.
austin wrote:
ISE ignores clock domain crossing (Vivado does not, but Vivado only supports 7 series and later devices). Do you have any unidentifed clock crossings that require synchronizers?
Yes, I do. As mentioned above I synchronize my handshake signals between clock domains using simple level synhronizers (since I'm not doing anything fancy like transforming pulses). I am also synchronizing the de-assert of my asynchronous system reset in both clock domains using standard reset bridges, which are basically just level synchronizers.
Interestingly, the timing report containing unconstrained path info tells me that one constraint was not met whereas the other one does not. It also concludes that the maximum frequency is lower than 100MHz, but gives the same result for the system clock. If I've understood correctly, this is due to the fact that there is an unconstrained path with maximum combinational path delay larger than 10ns. I had a look at this path (there are a few of the same type) and it is a path that I don't think needs to be constrained, so I wouldn't see this as the issue.
Albeit having looked at the timing reports, I wouldn't exclude that I've missed something, simply because I haven't dealt with such problems until now. So, I'm not sure whether or not it would be helpful to attach both the standard verbose timing report and the one including unconstrained paths...but perhaps someone could point me to something that might seem fishy..?
One thing I will do is continue to try and isolate the location of the problem using timing simulations or possibly stripping the logic of certain components and checking the behavior of the implemented design.
Best regards,
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Revision: 4859
Author: [email protected]
Date: 2009-02-05 10:15:22 -0800 (Thu, 05 Feb 2009)
Log Message:
-Fix packaging timing issue that was caused by the rebuilding of the air applicationupdater. The recompiled files would get laid down properly only to have the old files put back down on top of them. I also made sure the build directory was removed after updateAIR ran so it would not be included in the package
-removed bundles.properties from the wireframe project
bug:SDK-19128
qa:yes
doc:no
checkintests:pass
Ticket Links:
http://bugs.adobe.com/jira/browse/SDK-19128
Modified Paths:
flex/sdk/branches/i10/build.xml
flex/sdk/branches/i10/frameworks/build.xml
Removed Paths:
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NVIDIA GEFORCE 8500 cardI've used VideoReDo in the past, which I believe has some similar strategies to Womble. I found when I tested streams, that there were often problems in the source streams, and that the fix was not 100 percent.
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I am using an RS232 to control an older model Power Supply (OXFORD PS 120-10).
I have successfully written several VI's that all work, the only problem is that VISA Read takes WAY too long. I'm talking 10's of seconds to refresh. I need it have it refreshing in milliseconds or at least tens of seconds for the measurements we need. All of the VI's I have written have the same timing issue.
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Please help if you can, I've only been working with LabVIEW for a few weeks and am very must still in the learning process.
Thanks!
Solved!
Go to Solution.
Attachments:
READandWRITE timing test.vi 14 KB
READandWRITE timing test.vi 14 KBDo you have the communications protocol for the power supply? If you do not have everything right, you will have problems with communications.
Tens of seconds is a clue that you may be getting timeout errors because the default timeout is 10 seconds. Try placing an inidicator on the error out wire inside the loop (after Read) to see if an error occurs on any iteration. The way you have the VI set up you only see the error on the last iteration of the loop.
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Questions about phase difference (possible timing issue) RC circuit
Hello,
Below is the program I am using to measure the phase difference in an RC circuit. Simply put I generate a 2kHz sine wave in LabView and send it to the circuit using an Analog output. Then I measure the output sine wave using an analog output.I also measure this using n oscilliscope. I cna clearly measure the phase difference with the oscilliscope and know it to be approximately 1.4 radians.
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Solved!
Go to Solution.
Attachments:
RC Circuit Test.vi 271 KBI would certainly acquire two signals. Feed the analog output right back into an analog input and then your filtered signals in another.
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