I have one application that has requirement to do low and high speed acquisition. I want to change sample rate while running. BUT... I have E series Device

Question

I am writing control software for a process that is usually dull and
requires only 10 Hz acquisition rate.  At particular times during
the sequence, however, we are interested in looking at a couple of
channels at 1000 Hz.  My approach so far is to configure my
Buffered DAQ to run at the higher rate at all times.  When we are
in the 'high-speed DAQ' mode, the program logs every point to
disk.  In the 'low-speed' mode, I am picking off every nth (in
this case, 10th) point to log to disk.  At all times, I update my
GUI indicators on the front panel at a maximum of 4 times per second (I
find that anything faster results in an uncomfortable display), so I
fill up a FIFO with data in my acquisition / logging loop, and read the
FIFO in the display loop.  The data in my GUI display can be up to
250 milliseconds off, but I find this acceptable . As a side note, I
need buffered Daq with hardware timing, as software timing results in
lost data at 1000 Hz.
This all works fine and dandy, but I am convinced that it is not the
most elegant solution in the world.  Has anyone developed a
buffered DAQ loop where the scan rate can be adjusted during
operation?  I would like to change the rate of the E-Series card
rather than relying on down-sampling as I am now doing. 
The reason I have concern is that at the moment I am simulating my AI
using MAX and when running the down-sampling routine, I consistently
miss a particular event on the simulated data becuase the event in
question on the simulated data always occurs at the same 'time', and I
always miss it.  Granted, while it is unlikely that my measured
signal and my acquisition are perfectly synchronized in the real world,
this particular situation points out the weakness in my approach.
More than anything, I am looking for ideas from the community to see
how other people have solved similar problems, and to have you guys
either tear apart my approach or tell me it is 'ok'.  What do you
think?
Wes Ramm, Cyth UK
CLD, CPLI

Answer 1

Adding to Alan's answer:
One of the problems that comes with these tricks for variable-rate acquisition is being able to match up sample data with the time that it was sampled. 
If you weren't using either of E-series board's counters, there is a nifty solution to this!  You'll be using 1 of the counters to generate the variable-rate sampling clock.  You can then use the 2nd counter to perform a buffered period measurement on the output of the 1st counter.  This gives you a hw-timed measurement of every sampling interval.  You would need to keep track of a cumulative sum of these periods to generate a hw-accurate timestamp value for each sample.
Note:  the very first buffered period measurement is the time from starting the 2nd counter until the first active edge from the 1st.  For your app, you should ignore it.
-Kevin P.