Intelligent Controller Parameterization

Attempting to use Intelligent Controller Parameterization but I am recieving a licensing error. The software seems to not be able to identify the ssdivd.lic license, and asks me for the directory location of the file. After searching my computer and local server it appear I dont have the license. I have contacted the company now multiple time with no reply... Any suggestions on where i may be able to find/Purchase the appropriate licensing. -Thanks

Since this is not a LabVIEW question, you should contact the company directly for this third-party add-on.
Look at the overview tab here for contact information
LabVIEW Champion . Do more with less code and in less time .

Similar Messages

New Ultra320 disks die in D1000

I have a D1000 I am trying to populate with newish generic ST3300007LC 300GB Ultra320 SCSI drives. The setup works OK for a few seconds after boot or even a few minutes, but eventually the glm/scsi driver backs off from 40MB to 2MB/sec, making the device basically useless (see the errors below.) I have swapped out the D1000 chassis, D1000 controllers, disks, cables, and controller and consistently the right hand side of the D1000 is what dies. The left hand side keeps working at 40MB/sec.
1) The manual does not illustrate it, but I am running the D1000 "split" with one cable to each interface of the dual channel HVD controller. (It only shows the split D1000 going to two separate hosts) I have wo dual channel HVD controllers in the host, so I tried both and also tried running each side of the D1000 to separate controllers. Both configs die.
2) Are the new 300GB Ultra 320 drives just not going to work in the D1000? Is there an sd.conf parameter that can be set?
WARNING: /pci@1f,2000/scsi@1 (glm4):
Target 2 reducing sync. transfer rate
WARNING: ID[SUNWpd.glm.sync_wide_backoff.6014]
WARNING: /pci@1f,4000/scsi@2 (glm2):
genunix: [ID 936769 kern.info] glm4 is /pci@1f,2000/scsi@1
scsi: [ID 107833 kern.warning] WARNING: /pci@1f,2000/scsi@1 (glm4):
SCSI bus DATA IN phase parity error
glm: [ID 663555 kern.warning] WARNING: ID[SUNWpd.glm.parity_check.6010]
scsi: [ID 107833 kern.warning] WARNING: /pci@1f,2000/scsi@1 (glm4):
Target 2 reducing sync. transfer rate
glm: [ID 923092 kern.warning] WARNING: ID[SUNWpd.glm.sync_wide_backoff.6014]
scsi: [ID 107833 kern.warning] WARNING: /pci@1f,2000/scsi@1 (glm4):
SCSI bus DATA IN phase parity error
glm: [ID 663555 kern.warning] WARNING: ID[SUNWpd.glm.parity_check.6010]
scsi: [ID 107833 kern.warning] WARNING: /pci@1f,2000/scsi@1 (glm4):
Target 2 disabled wide SCSI mode
glm: [ID 681974 kern.warning] WARNING: ID[SUNWpd.glm.sync_wide_backoff.6012]
scsi: [ID 107833 kern.warning] WARNING: /pci@1f,2000/scsi@1 (glm4):
Target 2 reverting to async. mode
glm: [ID 802533 kern.warning] WARNING: ID[SUNWpd.glm.sync_wide_backoff.6013]
scsi: [ID 193665 kern.info] sd14 at glm4: target 2 lun 0

Yep, teminators and cables have been swapped.
I am reserarching to see if there are any sd.conf parameters I might be able to use to "fix" the SCSI bus at 40MB or even 20MB/sec, or at least prevent it from falling back all the way to SCSI-1. I recall doing this at some point long long ago to work around some similar bugs.
I have not tested with small, old disks - they are all Ultra 160, so who knows?
Right now the individual disks are all initially syncing up at 40MB, according to prtconf -v, so I assume there is just some kind of differential to LVD interface conversion inside the D1000, and not any kind of intelligent controller.
So using a single dual-channel controller card makes perfect sense. With both sides of the D1000 split, there is no problem achieving 40MB/sec on each side of the D1000, with all disks of the D1000 on the same channel, aggregate performance is limited to 40MB/sec for all disks in the bus. The PCI channel can easily keep up with 80MB/sec aggregate performance, and I can get achieve this until one of the channels errors out and falls back to SCSI-1.
You're not protected from a controller failure, but you're not protected from an enclosure failure eiither if you use two controllers. Unless of course it's an "unsupported" config this way and for some reason or another is not reliable.
I readily admit the configuration is a kludge, and not substantially cheaper than a modern SATA based array. But it's what my bosses would let me buy, so I'm stuck with it.

NGSA2 c code in my single board RIO

Hi,
I want to introduce several c code in order to have an intelligent controller in my single board RIO. I have read that i have to put it in a shared library in the VxOS of the RIO, but the instructions to do this are quite "dirty". Is not there any other solution??

Peper,
You are actually referencing the previous generation of sbRIO's manual in this post. It is a bit confusing at that manual was labeled 963x. If you go to the sbRIO-9636's product page, you can select "Resources" and get to the prodcut manuals from there. Here is the sbRIO-9636's manual.
The Sleep I/O item allows C Series module to enter a sleep mode, not the sbRIO controller itself; therefore, the sbRIO-9636 does not have a Sleep I/O item under the FPGA target in the LabVIEW Project.
If you want to go into a lower power state, you can stop the FPGA bitfile from running which should lower the power consumption (you can do this with the FPGA Abort invoke node with the FPGA Interface that runs on RT).
Tannerite
National Instruments

Keyboard controller and Intelligent Instruments

Hello
I am looking at buying an external (music) keyboard for my iPhone to run GB.
I am quite aware that I can easily run the Keyboard instruments with no problem.
My question is running Intelligent Instuments with the External Keyboard.
As we know, these instruments are CHORDED and laid out on their proper instruments (not piano-ish).
IF someone with an externally plugged in keyboard can possibly relay that bit of info to me, it would definitely be appreciated.
Regards
Ralph

For everyone's information, the answer is YES,
External Keyboard controllers can easily run Smart INSTRUMENTS.
Regards

R series intelligent DAQ, NI-Compact RIO , NI single board RIO

Hi,
I'm in the phase of choosing an FPGA to use in programming some DSP modules. The thing is that while I'm reading about the different technologies to be used, I find it difficult to know how will these devices be connected to my PC and programmed. For example, when using R series intelligent DAQs, do I have to get a compact RIO as well , or can I get a PCI-bus R - DAQ and connect it to the PC.
Some clarification of how to use each of these devices will be appreciated.
Thanks,
Walid

Just to elaborate on what Venkatesh said
With a compact RIO you will connect your PC to the RIO using Ethernet, direct through a cross over or through a network hub.
This introductory video will teach you how to install, configure, and program the latest NI CompactR...
A PCI R series card, just plugs straight into your Windows computer PCI slot.
A PXI card will plug into a PXI chassis and will give you one of 2 programming options
1. If you have a PXI system controller running Windows XP with the appropriate drivers and version of LV you can program the FPGA directly in the PXI chassis
2. You can connect to the PXI chassis through Ethernet and program the FPGA from there.
Compiling and deploying your program will work the same no matter what connection you use.
-Hunter

Impact of Controller Policy on ASM

This is to share with everyone my discoveries in regard to Controller Policy for ASM (Automatic Storage Management) in a JBOD (just a bunch of disks) configuration.
As it turns out, it makes a big difference in performance how you set your controller policy. I tested various settings for the READ POLICY: ADAPtive read-ahead, (always) Read-Ahead, or NO-Read-Ahead; and CACHE POLICY: Cache I/O, or Direct I/O. WRITE POLICY was kept at Write-Back, with Write-Through not tested (Warning).
This test showed the best performance is attained if you set Read Policy to NO_READAHEAD, Cache Policy to DIRECTIO, and Write Policy to WRITEBACK. The SQL used are more suitable for OLAP than OLTP. (Time is in min:sec)
ADAP-------ADAP--------NO-RA-------RA------------Read Policy
CACHEIO--DIRECTIO--DIRECTIO--DIRECTIO--Cache Policy
9:13----------6:45----------5:19------------6:50-------------Complex CTAS 3tbl join
6:49----------5:58----------3:53------------7:02-------------Full Table Scan 120mil recs
4:41----------3:42----------3:39------------3:44-------------Full Scan of IOT Table 100mil rec
These tests were conducted on two Dell PowerVaults with 28 x 136 GB 15K RPM drives and one PERC RAID controller set to eliminate any RAID so ASM would provide all mirroring by scattering 1 MB Allocation Unit copies over various disks. Other specs: Windows Server 2003 SP2, Dell 1850 3.6 GHz Xeon PCU. Oracle 10g Standard Edition One. Parameter dbfile_multiblock_read_count is set to read 1 MB.
Your configuration will not match mine, but this test does show that it is worth the time to invest in empirical measurements of controller policy performance. DO NOT TAKE CONTROLLER POLICY FORGRANTED AND GO WITH THE DEFAULT POLICY OR ANY OUT OF THE BOX SOLUTION. This test showed that READ-AHEAD IS HARMFUL FOR ASM with 1MB AU and 1 MB dbfile_multiblock_read_count. I speculate that either Oracle ASM may be issuing its own intelligent read-ahead, or the ASM scatter of 1MB chunks renders single-disk read-ahead useless & excessive, or both.
I am very interested in reading your discoveries in tuning controller policy for ASM.

1: Why not try with 2 PERC adapters ? The single adapter would be a SPOF and a possible bottleneckGood question; and are correct. Normally we would use 2 controllers with 2 PowerVaults and cross-hatch the 4 cables. Howerver, in this case we are planning to grow to 4 PowerVaults, 4 cables, and 2 PERCs (the max), so I need to plan on 2 PV per PERC.
2. Can we see your init.ora Sure. We do data mining, so our settings favor high throughput with minimal availability needs. Due to the amount of data moved via single-threaded execution (this is SE1) we are I/O constrained.
processes = 275
sessions = 308
__shared_pool_size = 176160768
__large_pool_size = 8388608
__java_pool_size = 159383552
java_pool_size = 159383552
sga_target = 1375731712
db_block_size = 16384
__db_cache_size = 838860800
db_keep_cache_size = 16777216
db_recycle_cache_size = 159383552
compatible = 10.2.0.3.0
log_buffer = 15244288
db_file_multiblock_read_count= 64
db_create_file_dest = +DATA
undo_management = AUTO
undo_tablespace = UNDOTBS1
undo_retention = 36000
job_queue_processes = 10
cursor_sharing = FORCE
open_cursors = 300
optimizer_mode = FIRST_ROWS_1000
optimizer_index_cost_adj = 1
optimizer_index_caching = 75
query_rewrite_integrity = TRUSTED
pga_aggregate_target = 1560281088
optimizer_dynamic_sampling= 3
3. Can we see the DDL for the ASM Disks/Diskgroups and the tablespace definitions?Using diskpart.exe the disks were all set as:
create partition primary size=139264 align=64
One large +DATA disk-group was made over all of these disks, placing each disk in its own failure-group, with normal redundancy.
CREATE SMALLFILE TABLESPACE "SYSTEM"
DATAFILE '+DATA(DATAFILE)' SIZE 5120M
AUTOEXTEND ON NEXT 10240K
MAXSIZE 65535M
LOGGING
EXTENT MANAGEMENT LOCAL
SEGMENT SPACE MANAGEMENT MANUAL;
CREATE SMALLFILE TABLESPACE "SYSAUX"
DATAFILE '+DATA(DATAFILE)' SIZE 5120M
AUTOEXTEND ON NEXT 10240K
MAXSIZE 65535M LOGGING
EXTENT MANAGEMENT LOCAL
SEGMENT SPACE MANAGEMENT AUTO;
ALTER DATABASE ADD LOGFILE GROUP 1 ('+DATA(ARCHIVELOG)') SIZE 10240M;
ALTER DATABASE ADD LOGFILE GROUP 2 ('+DATA(ARCHIVELOG)') SIZE 10240M;
ALTER DATABASE ADD LOGFILE GROUP 3 ('+DATA(ARCHIVELOG)') SIZE 10240M;
CREATE BIGFILE TABLESPACE "REF1_DATA"
DATAFILE'+DATA(DATAFILE)' SIZE 150G
AUTOEXTEND ON NEXT 10G
MAXSIZE UNLIMITED
NOLOGGING
EXTENT MANAGEMENT LOCAL
UNIFORM SIZE 64M
SEGMENT SPACE MANAGEMENT AUTO;
CREATE BIGFILE TABLESPACE "USER_DATA"
DATAFILE'+DATA(DATAFILE)' SIZE 350G
AUTOEXTEND ON NEXT 5G
MAXSIZE UNLIMITED
LOGGING
EXTENT MANAGEMENT LOCAL
SEGMENT SPACE MANAGEMENT AUTO;
CREATE BIGFILE TABLESPACE "USER_INDEX"
DATAFILE'+DATA(DATAFILE)' SIZE 100G
AUTOEXTEND ON NEXT 5G
MAXSIZE UNLIMITED
NOLOGGING
EXTENT MANAGEMENT LOCAL
SEGMENT SPACE MANAGEMENT AUTO;
CREATE BIGFILE TEMPORARY TABLESPACE "TEMP"
TEMPFILE '+DATA(DATAFILE)' SIZE 184320M
AUTOEXTEND ON NEXT 640K
MAXSIZE 67092480M
EXTENT MANAGEMENT LOCAL UNIFORM SIZE 1024K;
ALTER DATABASE DEFAULT TEMPORARY TABLESPACE "TEMP";
CREATE BIGFILE UNDO TABLESPACE "UNDOTBS1"
DATAFILE '+DATA(DATAFILE)' SIZE 143360M REUSE;

I need find out the most intelligent approach.....

I'm working an environment where Servel Production databases are running at ORacle 8i DB Server.
I'm also managing their backup at Oracle Standby Server.
I need to find out the most intelligent approach to add disk space to a PRIMARY-STANDBY Production Environment.
WE ARE USING WINDOWNS NT SERVER + ORACLE 8i.

The optimal method for setting up Oracle storage is to use a multi-channel RAID controller and set up several RAID 0+1 drive sets, this allows you fine grained control of I/O.
Now of course this is going to be expensive, so the real over-riding factor is what is the budget?
Your choices are (cheapest to most expensive).
Single Drive in the server.
RAID set in the server.
External RAID Arrays attached to the server.
Network Attached Storage (NAS) (never a good choice for Oracle, unless you put it on a private network utilizing Gb NIC cards).
Storage Area Network (SAN).

Thermal event with intelligent throttling disabled

Hi all
We have one Oracle unbreakable Linux installed on a HP DL380 G5. Since the install we've been getting error message Tmid Thermal event with intelligent throttling disabled.
We logged it with HP thinking it could be the memory, HP replaced the motherboard. Yet the message has not cleared. The server has 32GB memory. We removed a pair of memory en tested the server again. still the message appear. We repeated the process with all the modules. We then replaced it with new spare 2GB memory and still the message came back. Then we did a memtest still no luck.
I am now starting to wonder if the problem does not lay with the Kernel. (it seems to happen when our Oracle DBA are importing migrated tables and data)
Any ideas or steps to do more test or fix this issue. Not sure if we want to disable the message of showing.
Here is some info of the server, memory, processors, kernel version and the error message:
Linux version 2.6.18-92.1.22.0.1.el5 ([email protected]) (gcc version 4.1.2 20071124 (Red Hat 4.1.2-42)) #1 SMP Tue Dec 16 16:54:25 EST 2008
arch
x86_64
meminfo
MemTotal: 32831032 kB
MemFree: 325276 kB
Buffers: 699700 kB
Cached: 30022748 kB
SwapCached: 90040 kB
Active: 17000236 kB
Inactive: 14887732 kB
HighTotal: 0 kB
HighFree: 0 kB
LowTotal: 32831032 kB
LowFree: 325276 kB
SwapTotal: 8385920 kB
SwapFree: 8295880 kB
Dirty: 600 kB
Writeback: 0 kB
AnonPages: 1075372 kB
Mapped: 3769940 kB
Slab: 401696 kB
PageTables: 174980 kB
NFS_Unstable: 0 kB
Bounce: 0 kB
CommitLimit: 24801436 kB
Committed_AS: 7798452 kB
VmallocTotal: 34359738367 kB
VmallocUsed: 267100 kB
VmallocChunk: 34359470055 kB
HugePages_Total: 0
HugePages_Free: 0
HugePages_Rsvd: 0
Hugepagesize: 2048 kB
free -m
total used free shared buffers cached
Mem: 32061 31738 323 0 684 29326
-/+ buffers/cache: 1727 30333
Swap: 8189 87 8101
cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 23
model name : Intel(R) Xeon(R) CPU X5260 @ 3.33GHz
stepping : 6
cpu MHz : 3333.342
cache size : 6144 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm constant_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr lahf_lm
bogomips : 6671.14
clflush size : 64
cache_alignment : 64
address sizes : 38 bits physical, 48 bits virtual
power management:
processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 23
model name : Intel(R) Xeon(R) CPU X5260 @ 3.33GHz
stepping : 6
cpu MHz : 3333.342
cache size : 6144 KB
physical id : 0
siblings : 2
core id : 1
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm constant_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr lahf_lm
bogomips : 6666.59
clflush size : 64
cache_alignment : 64
address sizes : 38 bits physical, 48 bits virtual
power management:
[cat /var/log/messages | grep -i thermal
Apr 22 13:46:28 kernel: EDAC i5000 MC0: >Tmid Thermal event with intelligent throttling disabled
Apr 22 13:46:29 kernel: EDAC i5000 MC0: >Tmid Thermal event with intelligent throttling disabled
Apr 22 13:46:31 kernel: EDAC i5000 MC0: >Tmid Thermal event with intelligent throttling disabled
Apr 22 13:46:32 kernel: EDAC i5000 MC0: >Tmid Thermal event with intelligent throttling disabled
Apr 22 13:46:38 kernel: EDAC i5000 MC0: >Tmid Thermal event with intelligent throttling disabled
Apr 22 13:46:41 kernel: EDAC i5000 MC0: >Tmid Thermal event with intelligent throttling disabled
Apr 22 13:46:42 kernel: EDAC i5000 MC0: >Tmid Thermal event with intelligent throttling disabled
Apr 22 13:46:43 kernel: EDAC i5000 MC0: >Tmid Thermal event with intelligent throttling disabled

Subject:
kernel: EDAC i5000 MC0: >Tmid Thermal event with intelligent throttling disabled
Findings:
I spend nearly the whole day yesterday investigating this error. This is a bug in the current Kernel Version.
(Linux version 2.6.18-92.1.22.0.1.el5 ([email protected]) (gcc version 4.1.2 20071124 (Red Hat 4.1.2-42)) #1 SMP Tue Dec 16 16:54:25 EST 2008)
This bug is currently under investigation by Red hat Bugzilla.
Breakdown of Error:
error code is EDAC i5000 MC0
Edac is a memory stat tool in the kernel monitoring the RAM Memory for ECC memory
i5000 is the chipset memory controller for Intel
This error seems to happen the majority of the time on HP DL380 G5 and some servers of the Dell range.
Bios has its own memory stat tool. At the moment the EDAC stat tool is conflicting with the Bios monitor.
What we done:*
We done a memtest over 6 hr and it was successful
we tested the memory modules by removing pairs at a time
Then we put the original memory back in. (Spare memory)
HP replace motherboard
Still the message appear
Solution:
As the EDAC is only a memory Stat tool for the kernel and it does not have any impact on the OS or the server(none critical). We can blacklist (stop the error message for popping up) it until the next kernel release when this bug should be fixed.
Bios are already monitoring the memory via Bios Any memory failure or thermal event will be reported
The workaround for this problem is to prevent the i5000_edac module from loading. To do this, add the following line to the /etc/modprobe.d/blacklist file then reboot server boot.
Thanks for both you guys for pointing me in the right direction.
Edited by: user10737360 on 24-Apr-2009 02:13

Usage of PID controller instead of ON OFF controller

respected sir,
I pursuing btech final year in the stream of instrumentation.sir i have a doubt while go through my project,can i use PID controller instead of using ON OFF CONTROLLER. would you please suggest me the possible ways which are going to implement in my final project intelligent wheel chair.i am eagerly waiting for your valuable acknowledgement.
thank you,
with warm regards,
BOMMAREDDY

Hi!
I am not sure if I completely understand the question but if you are wanting to do autotuning for PID there is actually a VI that will do it for you. It is called PID Autotuning.vi and can be found under the PID Control pallete in LabVIEW. The LabVIEW Help file also contains more detailed information on the inputs and outputs to the VI.
Carlton
CLD

Mega 865 with a ATA Controller card

I have a Mega 865 with a P4 3.0 GHz, 1GB RAM and a Seagate HD running on Windows XP sp2.
My server crashed so I put the Promise ULTRA 100 TX2 Controller card in the PCI slot after I removed the cover of the Mega. I have 3 disks that get the power from an external power supply connected to the Controller card. When I start the Mega 865 and open Windows Explorer, I only see Total Size 5 MB on each of the 4 partitions that are on the 2 harddisks connected to the IDE 2. When I check through the Control Panel, Computer Management, Disk Management I can see the entire disks. I can enter each folder on these disks, but the PROBLEM is that I can not put any more data there. I get the message "There is not enough free disk space".
Because this controller card works in other computers and so does the disks I think that there is a problem with the Mega 865's motherboard and/or it's BIOS.
Is there anyone who have seen or heard about something like this before ?
Or are intelligent enough to solve my problem.
I don't have the money at the moment to buy a new server
a picture: http://www.pbase.com/obibobi/image/35413700/original
Edited to be more clear: the 3 extra disks are connected to a EXTERNAL power supply.

I would say further obibobi's actions probably depend on whether the data on HDD-s needs to be preserved or not.
Since I have never heard of "write protect" function in RAID controllers, the described situation seems like a h/w problem to me. having said that, I must admit though that I have never dealt with Promise stuff so far, not to mention ATA RAID controllers.. :(
In case if existing data on disks may be lost, best way forward seems to flush the entire configuration of the Promise controller and to try to re-configure it. Along with that, it may be useful to reduce the existing power consumption of Mega PC as much as possible (e.g. removal of AGP card, clocking down the CPU).
It is not entirely impossible that PSU of Mega can't handle the Promise card...
If existing data on HDD-s must be preserved at all cost, I would try to find a better host system for this disk array...

Yamaha 01V MIDI Controller Map - Any interest?

Hello
The Yamaha 01V classic (i.e. not 01V96) is not supported directly under Logic Pro 8, however a passable workaround should be possible by:
1. Assigning an appropriate set of MIDI send messages to each control change in the 01V.
2. Developing an Automation Quick Access set in Logic to respond to these MIDI control changes.
Do you think it would be possible to make an Automation Quick Access which is generic and thereby would respond intelligently to track re-shuffles, track additions and similar? e.g. fader number one on the 01V would always control the volume of "sequencer track 1" rather than "audio channel 1".
The alternate solution if a generic set isn't available is to set up a template song with a track count requisite to song needs, but this is less than ideal because the number of channels/software instruments/buses etc usually varies between projects!
Would love to hear feedback from interested parties.
Carl

Automation Quick Access is for using one controller, like a mod wheel or slider, to control any current automation parameter.
There is no such thing as an "Automation Quick Access set". There is only one automation quick access parameter to learn.
What you want is to use the controller assignments window to create a set of custom controller assignments. Yes, you can handle bank offsets for faders and things like that. make sure you read the control surfaces manual and section, and understand what modes and zones are, and the available functionality in the controller assignments window.
Doing a "complete" (-ish) controller assignments set correctly implementing bank offsets, plugin parameters, mixes parameters, audio instrument parameters and so on is not trivial, and some of the more sophisticated functionality that you get with the Mackie Control such as feedback and other niceties you can't use wihout a custom programmed control surface module (which only Apple can make).
Also be aware that the controller assignments are vey buggy. Do it carefully, make lots of backups of your control surface prefs (these are only saved on exit of Logic) and take it slowly.
Good luck!

NEURAL CONTROLLER IN LABVIEW

Is it possible to implement NARMA-L2 Neuro controller in LABVIEW?
How to implement speed control of DC motor based neural network using LABVIEW?

Here's an example of neural network with backpropagation method based on a conference paper: “LabVIEW based Intelligent Control for Speed Regulation of Electric Motor” by Dr. Jerome et al
Prof. Ponce-Cruz's book (listed below) also provides great resrouces on the topic.
Implemetation of Neural Network on Labview 8.5
http://decibel.ni.com/content/docs/DOC-5381
Intelligent Control Systems with LabVIEW
http://decibel.ni.com/content/docs/DOC-9392
Andy Chang
National Instruments
LabVIEW Control Design and Simulation

Unable to capture button event in pageLayout Controller

Hi Guys,
I have the following layout
pageLayout
pageLayoutCO (controller)
----header (Region)
----------messageComponentLayout (Region)
-----------------MessageLovInpurt
-----------------MessageChoice(Item)
-----------------MessageTextInput
-----------------MessageLayout
----------HideShow (Region)
-----------------MessageLovInpurt(Item)
-----------------MessageChoice(Item)
-----------------MessageTextInput(Item)
-----------MessageComponentLayout (Region)
-----------------MessageLayout
------------------------SubmitButton(ID:SearchBtn)
------------------------SubmitButton(ID:ClearBtn, fires partial action named clear)
-----------header(Region)
I am not able to capture the event fired by the button ClearBtn in the controller of the pagelayout.....
The two methods I used as follows aren't worked:
if ("clear".equals(pageContext.getParameter(OAWebBeanConstants.EVENT_PARAM)))
if (pageContext.getParameter("ClearBtn") != null) {
what should i do in order to capture the button event in the pageLayout Controller
Thanks in advance
Mandy
Edited by: user8898100 on 2011-8-2 上午7:49

Mandy,
Its really strange that its not able to caputure the event in CO.
Below is the way in which we handle to Submit action at CO level.
/Check whether ClearBtn is same in case too.
if(pageContext.getParameter("ClearBtn")!=null){
System.out.println("Inside the Clear Btn Action");
Regards,
Gyan

How can I use one motion controller to control two robotic independently?

the help document says :
Note Configuring and clearing buffers is a processor-intensive operation on the motion controller that requires the allocation and deallocation of memory. You should configure and clear buffers only when motors are not moving and onboard programs are not running. For example, if you wish to execute three simultaneous contouring operations on axis 1, axis 2, and vector space 1 (with axes 3 and 4), you should first configure all three buffers before starting any of the operations. You can start the contour operations independently, and at different times, but should wait until all operations are complete before clearing any of the buffers.
and i tried to conduct two contouring operation on two vector space. and tried to clear or configuring buffer for one vector when another one is still moving. so that i can start or end the movement at any time i want,and it is ok.no error. but when i tried add a buffer breakpoint output along with each vector movement. the bp doesn't work if the other vector is running . is there anyway to solve this problem.

I think you've misunderstood what the dns attribute is for. The dns attribute returns the hostname of the client accessing your website, not the hostname of the website that linked to your website.
For example, when someone using the Comcast ISP goes to a malicious website at example.com that loads images from your website at www.amigoo.net, the dns attribute will be something like "c-1-2-3-4.ca.comcast.net", not "example.com". ACLs are used for authentication and authorization of clients (not the websites those clients chose to visit), and they don't provide the functionality you're looking for.
If I understand correctly, you want to prevent websites other than amigoo.net from linking to files in your d:/webserver/imat/pics_upload directory. You can achieve this adding the following lines to your obj.conf configuration file:
<Object ppath="d:/webserver/imat/pics_upload/*">
<Client referer="*~*amigoo.net">
PathCheck fn="deny-existence"
</Client>
</Object>

Choosing a PXIe controller for streaming 200 MBps

Warning: This is a long post with several questions. My appologies in advance.
I am a physics professor at a small liberal-arts college, and will be replacing a very old multi-channel analyzer for doing basic gamma-ray spectroscopy. I would like to get a complete PXI system for maximum flexability. Hopefully this configuration could be used for a lot of other experiments such as pulsed NMR. But the most demanding role of the equipment would be gamma-ray spectroscopy, so I'll focus on that.
For this, I will need to be measuring either the maximum height of an electrical pulse, or (more often) the integrated voltage of the pulse. Pulses are typically 500 ns wide (at half maximum), and between roughly 2-200 mV without a preamp and up to 10V after the preamp. With the PXI-5122 I don't think I'll need a preamp (better timing information and simpler pedagogy). A 100 MHz sampling rate would give me at least 50 samples over the main portion of the peak, and about 300 samples over the entire range of integration. This should be plenty if not a bit of overkill.
My main questions are related to finding a long-term solution, and keeping up with the high data rate. I'm mostly convinced that I want the NI PXIe-5122 digitizer board, and the cheapest (8-slot) PXIe chassis. But I don't know what controller to use, or software environment (LabView / LabWindows / homebrew C++). This system will likely run about $15,000, which is more than my department's yearly budget. I have special funds to accomplish this now, but I want to minimize any future expenses in maintenance and updates.
The pulses to be measured arrive at random intervals, so performance will be best when I can still measure the heights or areas of pulses arriving in short succession. Obviously if two pulses overlap, I have to get clever and probably ignore them both. But I want to minimize dead time - the time after one pulse arrives that I become receptive to the next one. Dead times of less than 2 or 3 microseconds would be nice.
I can imagine two general approaches. One is to trigger on a pulse and have about a 3 us (or longer) readout window. There could be a little bit of pileup inspection to tell if I happen to be seeing the beginning of a second pulse after the one responsible for the trigger. Then I probably have to wait for some kind of re-arming time of the digitizer before it's ready to trigger on another pulse. Hopefully this time is short, 1 or 2 us. Is it? I don't see this in the spec sheet unless it's equivalent to minimum holdoff (2 us). For experiments with low rates of pulses, this seems like the easiest approach.
The other possibility is to stream data to the host computer, and somehow process the data as it rolls in. For high rate experiments, this would be a better mode of operation if the computer can keep up. For several minutes of continuous data collection, I cannot rely on buffering the entire sample in memory. I could stream to a RAID, but it's too expensive and I want to get feedback in real time as pulses are collected.
With this in mind, what would you recommend for a controller? The three choices that seem most reasonable to me are getting an embedded controller running Windows (or Linux?), an embedded controller running Labview real-time OS, or a fast interface card like the PCIe8371 and a powerful desktop PC. If all options are workable, which one would give me the lowest cost of upgrades over the next decade or so? I like the idea of a real-time embedded controller because I believe any run-of-the-mill desktop PC (whatever IT gives us) could connect and run the user interface including data display and higher-level analysis. Is that correct? But I am unsure of the life-span of an embedded controller, and am a little wary of the increased cost and need for periodic updates. How are real-time OS upgrades handled? Are they necessary? Real-time sounds nice and all that, but in reality I do not need to process the data stream in a real-time environment. It's just the computer and the digitizer board (not a control system), and both should buffer data very nicely. Is there a raw performance difference between the two OSes available for embedded controllers?
As for live processing of the streaming data, is this even possible? I'm not thinking very precisely about this (would really have to just try and find out), but it seems like it could possibly work on a a 2 GHz dual-core system. It would have to handle 200 MBps, but the data processing is extremely simple. For example one thread could mark the beginnings and ends of pulses, and do simple pile-up inspection. Another thread could integrate the pulses (no curve fitting or interpolation necessary, just simple addition) and store results in a table or list. Naievely, I'd have not quite 20 clock cycles per sample. It would be tight. Maybe just getting the data into the CPU cache is prohibitively slow. I'm not really even knowledgeable enough to make a reasonable guess. If it were possible, I would imagine that I would need to code it in LabWindows CVI and not LabView. That's not a big problem, but does anyone else have a good read on this? I have experience with C/C++, and some with LabView, but not LabWindows (yet).
What are my options if this system doesn't work out? The return policy is somewhat unfriendly, as 30 days may pass quickly as I struggle with the system while teaching full time. I'll have some student help and eventually a few long days over the summer. An alternative system could be built around XIA's Pixie-4 digitizer, which should mostly just work out of the box. I prefer somewhat the NI PXI-5122 solution because it's cheaper, better performance, has much more flexability, and suffers less from vendor lock-in. XIA's software is proprietary and very costly. If support ends or XIA gets bought out, I could be left with yet another legacy system. Bad.
The Pixie-4 does the peak detection and integration in hardware (FPGAs I think) so computing requirements are minimal. But again I prefer the flexibility of the NI digitizers. I would, however, be very interested if data from something as fast as the 5122 could be streamed into an FPGA-based DSP module. I haven't been able to find such a module yet. Any suggestions?
Otherwise, am I on the right track in general on this kind of system, or badly mistaken about some issue? Just want some reassurance before taking the plunge.

drnikitin,
The reason you did not find the spec for the rearm time for
the 5133 is because the USB-5133 is not capable of multi-record acquisition. The rearm time is a spec for the reference
trigger, and that trigger is used when fetching the next record. So every time you want to do another fetch
you will have to stop and restart your task.
To grab a lot of data increase your minimum record size. Keep in mind that you have 4MB of on board
memory per channel.
Since you will only be able to fetch 1 record at a time,
there really isn’t a way to use streaming.
When you call fetch, it will transfer the amount of data you specify to
PC memory through the USB port (up to 12 MB/s for USB 2.0 – Idealy).
Topher C,
We do have a Digitizer that has onboard signal processing
(OSP), which would be quicker than performing post processing. It is
the NI 5142
and can perform the following signal
processing functions. It is
essentially a 5122 but with built in OSP.
It may be a little out of your price range, but it may be worth a
look.
For more
information on streaming take a look at these two links (if you havn’t
already).
High-Speed
Data Streaming: Programming and Benchmarks
Streaming Options for PXI
Express
When dealing with different LabVIEW versions
it is important to note that previous versions will be compatible with new
versions; such as going from 8.0 to 8.5.
Keep in mind that if you go too far back then LabVIEW may complain, but
you still may be able to run your VI. If
you have a newer version going to an older version then we do have options in
LabVIEW to save your VI for older versions.
It’s usually just 1 version back, but in LabVIEW 8.5 you can save for
LabVIEW 8.2 and 8.0.
ESD,
Here is the link
I was referring to earlier about DMA transfers. DMA is actually done every time you call a
fetch or read function in LabVIEW or CVI (through NI-SCOPE).
Topher C and ESD,
LabVIEW is a combination of a compiled
language and an interpreted language.
Whenever you make a change to the block diagram LabVIEW compiles
itself. This way when you hit run, it is
ready to execute. During execution LabVIEW
uses the run-time engine to reference shared libraries (such as dll’s). Take a look at this DevZone article about
how LabVIEW compiles it’s block diagram (user code).
I hope all of this information helps!
Ryan N
National Instruments
Application Engineer
ni.com/support

Intelligent Controller Parameterization

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