Manually synthesizing the T1 core

Question

In the OpenSPARC T1 1.6 release, scripts are included to automatically synthesize T1 blocks. The synthesis can be done by Synplicity or by XST. The scripts to do this are named rsynp and rxil, respectively. The usage of these scripts is documented in the OpenSPARC T1 Design and Verification Guide.
These scripts are written in Shell language and Perl, so they will probably not run on a Windows machine unless a package of Unix utilities is installed. Such packages do exist, and some are free to download.
However, if you want to manually compile the design using ISE, for example, there are a few things to keep in mind. First of all, the original code had blocks which are not synthesizable. For example all the RAM models are not synthesizable. To make them synthesizable for FPGA, and to get them to map into Block RAM, we added several compile options into the code. When settting up a compile to ISE, the required option is to set the FPGA_SYN . This makes all the changes necessary for FPGA synthesis, including selecting RAM models that will map correctly into Xilinx block RAM. (Anyone who wants to map to Altera or other FPGA brands may need to modify the models a little bit). I don't know exactly how to select these compile options, but it's probably a command similar to "+define+FPGA_SYN+".
The above command will enable FPGA synthesis, but there are other options available to reduce the size of the core (see the Design and Verification Guide). For example the FPGA_SYN_1THREAD reduces the size of the core by reducing it from 4 threads to 1. This is required if you are synthesizing into a smaller FPGA like the XC4VFX50 found on the ML410 board. Other options allow for even more reduction in size.
Another problem encountered with Windows machines is the memory limitation. Windows XP machines are only able to address 3GB of physical memory, and the Virtual memory is limited to 2GB. If any process requires more than 2GB, it won't be able to complete. We ran into this exact problem when running place & route. Even though we put 4GB of RAM in the machine, it still ran out of memory (the Virtual memory was the limit). See the following web site for a possible workaround.
http://www.xilinx.com/support/answers/14932.htm
formalGuy

Answer 1

Here is a little more information on how to synthesize the T1 core manually from the ISE GUI. This is the procedure to follow if you can't use our automated scripts rsynp and rxil. (For exampe if you are on a Windows machine).
From the start menu, select ISE -> Project Navigator
From the Project Navigator GUI, select File->New Project ( the new project wizard may come up automatically if it is the first time you are running Project Navigator
Select a project name and the project path
Click next
The next window is Device Properties:
Select the correct Device, Package, and speed grade for your board.
Click next
The next window is Create new source.
Just skip this and click next
The next window is Add existing Source
Just skip this and click next
Finish the Wizard to create the project.
Now search for the following file which is a source list for the sparc core:
design/sys/iop/sparc/xst/sparc.flist
You need to select add sources and add each file from the file list to the project.
(There should just be some way to add the list, but I cannot figure out how to do it. Any ISE experts out there?)
Note that you may need to copy files ending with .behV to a new name ending with .v so that ISE recognizes the files a Verilog files.
The next step is to set the compile time macros: To do this:
1. Look for the ISE sub-window on the left labeled "Processes"
2. Find the "Synthesize-XST" entry in that window
3. Right click on that entry and select "Properties"
4. In the popup window "Process Properties - Synthesis Options,
select "synthesis options in the left window
5. Set the property display level to "Advanced"
6. In the right list scroll down to find the property
"Verilog Macros"
7. Type the value FPGA_SYN FPGA_SYN_1THREAD FPGA_SYN_NO_SPU FPGA_SYN_8TLB in that box.
Finally Run synthesis:
From the Processes window, right-click on Synthesize-XST and select Run in the popup Menu.
Hopefully, this gives enough details that you can figure the rest out.
formalGuy