Need help to interface InRevium's TB-FMCH-HDMI4K Board with ZC706 Eval board

Question

We (PathPartner Technology Consulting Services) have recently procured the above-mentioned card(from Inrevium) for supporting HDMI display (HDMI2.0 for 4K) for our FPGA-based Video Codec solution.
We are implementing this solution on ZC706 board (Zynq-7045 based)
We did get access to reference designs from Xilinx’s HDMI Reference Design lounge wherein the Reference design is targeted for KC705 evaluation board. It seemed feasible to implement the same design on ZC706 board since both the devices in KC705 and ZC706 use the same XCVR.
While implementing the design on ZC706 board, we could not generate bitfiles due to DRC violations. We did set the pin assignments made in XDC file targetting ZC706 (compared to KC705).
The DRC errors are:
[DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 1 net(s) are partially routed. The problem bus(es) and/or net(s) are IPI_INST/hdmi_ipi_i/hdmi_gt_0/inst/drurefclk_to_qpll.
[DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 2 out of 49 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DRU_CLK_P_IN, DRU_CLK_N_IN.
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
Delving further:
The HDMI 2.0 Design requires GT differential clock pairs for 3 of its clocks, the pins are as mentioned below:
In the reference design that is based on the KC705 board, these pins are connected to the approriate GT Differential clock pairs as below:
set_property PACKAGE_PIN C8 [get_ports HDMI_RX_CLK_P_IN]  (FMC_HPC_GBTCLK0_M2C_P on KC705)
set_property PACKAGE_PIN G8[get_ports DRU_CLK_P_IN] (SMA_MGT_REFCLK_P on KC705)
set_property PACKAGE_PIN E8 [get_ports TX_REFCLK_P_IN] (FMC_HPC_GBTCLK1_M2C_P on KC705)
But in case of ZC706 we could find only 2 GT pairs: FMC_HPC_GBTCLK0_M2C and FMC_HPC_GBTCLK1_M2C that corresponds to pins AD10 and AA8 respectively.
We could not find another differential clock pin on HPC connector with similar properties for DRU_CLK_P_IN.
We have set the constraints as follows:
set_property PACKAGE_PIN AD10 [get_ports HDMI_RX_CLK_P_IN] 
set_property PACKAGE_PIN AA8 [get_ports TX_REFCLK_P_IN]
and
set_property PACKAGE_PIN AF10 [get_ports DRU_CLK_P_IN]: Need to find an appropriate pin on ZC706 board
Please refer to the attached .xdc file that we are using for the bit file generation on ZC706 board (we have retained the file name similar to one used for KC705 in the reference design).
It will help us if we can find an alternative pin for the DRU_CLK_P_IN on ZCZ706 board
Another alternative would be: We do not need the RX port. Hence, if RX can be completely disabled, the RX CLK pin can be used for DRU_CLK_P_IN.  Need to know how RX can be disabled.
Looking forward for guidance in resolving the above-mentioned...
Thanks and Regards
Lalith
 

Answer 1

Hi Satish,
For the TB-FMCH-HDMI4K Card that we have procured from InRevium, we have got a reference design that is targetted for KC705 board. We have a ZC706 board and intend to get this card operational on ZC706. It seemed feasible since both the devices in KC705 and ZC706 use the same XCVR.
The HDMI 2.0 Design requires GT differential clock pairs for 3 of its clocks, the pins are as mentioned below:
In the reference design that is based on the KC705 board, these pins are connected to the approriate GT Differential clock pairs as below:
set_property PACKAGE_PIN C8 [get_ports HDMI_RX_CLK_P_IN]  (FMC_HPC_GBTCLK0_M2C_P on KC705)
set_property PACKAGE_PIN G8[get_ports DRU_CLK_P_IN] (SMA_MGT_REFCLK_P on KC705)
set_property PACKAGE_PIN E8 [get_ports TX_REFCLK_P_IN] (FMC_HPC_GBTCLK1_M2C_P on KC705)
But in case of ZC706 we could find only 2 GT pairs: FMC_HPC_GBTCLK0_M2C and FMC_HPC_GBTCLK1_M2C that corresponds to pins AD10 and AA8 respectively.
We could not find another differential clock pin on HPC connector with similar properties for DRU_CLK_P_IN.
We have set the constraints as follows:
set_property PACKAGE_PIN AD10 [get_ports HDMI_RX_CLK_P_IN] 
set_property PACKAGE_PIN AA8 [get_ports TX_REFCLK_P_IN]
and
set_property PACKAGE_PIN AF10 [get_ports DRU_CLK_P_IN]: Need to find an appropriate pin on ZC706 board
Please refer to the attached .xdc file that we are using for the bit file generation.
It will help us if we can find an alternative pin for the DRU_CLK_P_IN on ZCZ706 board
Another alternative would be: We do not need the RX port. Hence, if RX can be completely disabled, the RX CLK pin can be used for DRU_CLK_P_IN.  Need to know how RX can be disabled.
Looking forward for your guidance in resolving the same
Thanks and Regards
Lalith