Non-blocking write problem

Question

Hi all,
I have an HLS IP that is interracting with memory interface and other IPs. I want to always consume a fifo input to avoid potential deadlock, so here is what my design looks like:
void top(stream<data_t>& in, stream<data_t>& out, ......) {
#pragma HLS DATAFLOW
        static stream<data_t> fifo;
        moveTo(in, fifo);
        main_function(fifo, .......);
main_function is the main processing unit, which interracts with other IPs and memory interface. The input fifo "in" cannot be blocked, so I just have to consume it whenever possible. My solution is to have an internal fifo and use function "moveTo" to consume it. Here is what my moveTo function looks like:
void moveTo(stream<data_t>& in, stream<data_t>& out) {
#pragma HLS PIPELINE II=1
         if (!in.empty()) {
                  data_t temp = in.read();
                  out.write_nb(tmp);
However, in hardware, I can see that the input fifo "in" is valid but not ready, which means the consumer funciton is blocked. I also tried to manually detect full signal like
      if(!out.full())
             out.write(tmp);
, but it doesn't make any difference. Is there any recommended way to do what I am trying to achieve? I used a similar syntax when writing to an external fifo and it was working fine in hardware, so I am not sure why it is not working with internal one. Note that all the interfaces are eventually implemneted with "#pragma HLS resource core=AXI4Stream variable=" pragma to be synthesized as axi_stream interface. 
Thanks,
Jimmy

Answer 1

So I am able to figure out that when the "main_function" is blocked by a write to an external fifo, the start signal of "moveTo" will be disabled too despite the fact that the internal fifo is not full yet. Shouldn't DATAFLOW make each function independent from each other?