Odd values in SDK Export for Zynq with LPDDR2

Question

Hi all!
We are adapting our Zynq design for LPDDR2 and one of our more observant SW engineers found a number of peculiarities in the ps7_init.c generated from XPS.
The memory part we intend to use is the Micron MT42L16M32D1-25, a 64 Mbyte 800Mb/s device with 4 banks of 4Mwords by 32 bits. As this is not pre-programmed in XPS, I used the MT42L64M32D1KL-25 as a base for a Custom Memory Part  and altered the following parameters:
DRAM Device Capacity 2048 MBits -> 512 MBits
Bank Address Count 3 -> 2
Row Address Count 14 -> 13
…leaving everything else untouched. Effective DRAM Bus Width is 32 bits, Burst Length is set to 8 and Operating Freq (MHz) is 400.
The following registers initializations seem odd:
0XF8006004[11:0] = 0x00000061U
Average time between refreshes. This value computes to 6.2 us, 7.8 us should be OK according to the SDRAM data sheet. The value is on the safe side, so no big deal.
20140313: 2.5 [ns] * 32 * 0x61 = 7.76 [us]. The value is correct, my bad!
0XF8006018[4:0] = 0x0000000DU
Should be set to WL + BL/2 + tWR + 1 for LPDDR2, it looks like it is set to WL + BL/2 + tWR which is consistent for DDR2 or DDR3.
20140313: WL + BL/2 + tWR + 1 = 3 + 8/2 + RU(15/2.5) + 1 = 3 + 4 + 6 + 1 = 14  (0xE), am I wrong here? (RU = Round Up)
0XF8006018[31:28] = 0x00000007U
Should be set to the larger of tCKE or tCKESR or LPDDR2, or 15 ns. The value gives 17.5 ns, one clock cycle extra. The value is on the safe side, so no big deal.
0XF800601C[14:10] = 0x0000000AU
Should be set to WL + tWTR + BL/2 + 1 for LPDDR2, it looks like it is set to WL + tWTR + BL/2 which is consistent for DDR2 or DDR3.
 20140313: WL + tWTR + BL/2 + 1 = 3 + 7.5/2.5 + 8/2 + 1 = 11 (0xB), am I wrong here?
0XF800601C[31:28] = 0x00000007U
tRCD - AL. AL = Additive Latency doesn’t seem to be defined for LPDDR2, but the default value (0x8) maybe still should be there?
0XF8006030[31:16] = 0x00000003U
Value loaded into MR2 register, defining RL and WL. Should be RL6/WL3 -> 0100b, this value would give RL5/WL2.
20140313: Waiting for feedback on the WebCase.
0XF80060A4[31:22] = 0x00000040U
Number of cycles of NOP required after a ZQCS. tZQCS is 90 ns, so 0x24 should do, 0x40 is in excess.
Some of these may not have any adverse effects, but some seem like honest bugs. Question is, how well proven is the generated code from XPS? Should we go through every line with a fine-tooth comb or is there a fair chance that the device will operate once we get our new hardware? I haven't found any info on the forum and have filed a WebCase, but I thought I'd pop the question here as well. What is your experience?
The Zynq is a XC7Z020-1-CLG400. We are using ISE 14.7 running on a PC with 64-bit Windows-7.
Thanks!
/Lars
20140313: I have added some comments from the outcome of the WebCase, marked in maroon.

Answer 1

Hi again!
Does anyone beside us even use LPDDR2? It makes me wonder when the SW guys reported sporadic write errors and after spending a lot of time and numerous phone conferences with Xilinx tracking down signal integrity issues, we finally got to speak to a Xilinx expert in the US and he identified that the SDK export from XPS had omitted setting some of the essential control registers in the SDRAM controller, causing the drive strengths and slew rates on the data bus to be way off.
So users beware: If you still used ISE/XPS for Zynq development, you can't expect LPDDR2 to work.
Cheers!
/Lars