Par failing on EDK 11.4

Question

Dear forum members, I've designed a system on custom board using the spartan-6 lx45t device on EDK 11.4 using the base system builder. Following is the device utilization summary after map: 
   Number of LOCed IOBs                  97 out of 97    100%
   Number of SLICEXs                      4521 out of 6822   66%
   Number of Slice Registers             15138 out of 54576  27%
   Number used as Flip Flops          15136
   Number of Slice LUTS                  25539 out of 27288  93%
   Number of Slice LUT-Flip Flop pairs   25636 out of 27288  93% However, after PAR the following error is thrown and bit file is not generated.***************************************************************************************************************************************************************
ERROR:Xflow - Program par returned error code 30. Aborting flow execution...
make:
*** [__xps/system_routed] Error 1  I also get the following warnings during PAR. *************************************************************************************************************************************************************** WARNING:Par:288 - The signal mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/prioencdrOutput_pri<1> has no load.  PAR will not
   attempt to route this signal.
Starting Router
Wirelength Stats for nets on all pins. NumPins: 130211
Phase  1  : 136053 unrouted;      REAL time: 2 mins 3 secs
Phase  2  : 125020 unrouted;      REAL time: 2 mins 21 secs
Phase  3  : 86813 unrouted;      REAL time: 7 mins 13 secs
Phase  4  : 98510 unrouted; (Setup:5539693, Hold:6858, Component Switching Limit:0)     REAL time: 19 mins 11 secs ***************************************************************************************************************************************************************
WARNING:Route:441 - The router has detected a very high timing score (5469167) for this design. It is extremely unlikely the router will be
   able to meet your timing requirements. To prevent excessive run time the router will change strategy. The router will now work to
   completely route this design but not to improve timing. This behavior will allow you to use the Static Timing Report and FPGA Editor to
   isolate the paths with timing problems. The cause of this behavior is either overly difficult constraints, or issues with the
   implementation or synthesis of logic in the critical timing path. If you would prefer the router continue trying to meet timing and you
   are willing to accept a long run time set the option "-xe c" to override the present behavior.
  Intermediate status: 43159 unrouted;       REAL time: 49 mins 19 secs
  Intermediate status: 29897 unrouted;       REAL time: 1 hrs 19 mins 31 secs
Updating file: system.ncd with current partially routed design.***************************************************************************************************************************************************************
WARNING:Route:543 - Because this design is experiencing congestion, we recommend you run SmartXplorer with the "Use built-in SmartXplorer
   strategies for Congestion Reduction" radio button enabled in Project Navigator. For command line users, please run SmartXplorer with the
   -cr switch. This will run algorithms designed to avoid logic congestion. For more information on how to run SmartXplorer, please see the
   ISE Help (Project Navigator Users) or the Command Line Tools Users Guide (Command Line Users).
Phase  5  : 27042 unrouted; (Setup:21963466, Hold:6858, Component Switching Limit:0)     REAL time: 1 hrs 30 mins 19 secs
Total REAL time to Router completion: 1 hrs 30 mins 19 secs
Total CPU time to Router completion: 1 hrs 29 mins 47 secs
 *************************************************************************************************************************************************************** WARNING:Par:468 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in your design.
   Review the timing report using Timing Analyzer (In ISE select "Post-Place &
   Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
   Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
   are set in the tools for timing closure.
   Use the Xilinx "SmartXplorer" script to try special combinations of
   options known to produce very good results.
   Visit the Xilinx technical support web at http://support.xilinx.com and go to
   either "Troubleshoot->Tech Tips->Timing & Constraints" or "
   TechXclusives->Timing Closure" for tips and suggestions for meeting timing
   in your design.
Number of Timing Constraints that were not applied: 8*************************************************************************************************************************************************************** 
WARNING:Par:100 - Design is not completely routed.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.***************************************************************************************************************************************************************  
Total REAL time to PAR completion: 1 hrs 31 mins 3 secs
Total CPU time to PAR completion: 1 hrs 30 mins 24 secs
Peak Memory Usage:  553 MB
Placer: Placement generated during map.
Routing: Completed - errors found.
Timing: Completed - 5587 errors found.
Number of error messages: 0
Number of warning messages: 8
Number of info messages: 1
Writing design to file system.ncd
PAR done!
 Few days back the same warnings were thrown, but the bit file got generated, and system behaved as expected. But, since then the RTL of customIP core has changed, but by a very small amount. Please let me know, if someone faced the same problem and is there any workaround for it. Thanks in advance,Sumanth.

Answer 1

I am using the same part and get the same error. I do not believe my design is unbalanced or too highly mapped. It seems very possible that this may be a Spartan-6 LX45 issue, especially considering there are no other forum post about this and any other parts. The fact that both of us have the same problem with the same part and nobody else seems to is suspicious.   Device Utilization Summary:
   Number of BSCANs                          2 out of 4      50%
   Number of BUFGs                          10 out of 16     62%
   Number of BUFIO2s                         3 out of 32      9%
   Number of BUFIO2FBs                       2 out of 32      6%
   Number of BUFPLLs                         2 out of 8      25%
   Number of BUFPLL_MCBs                     1 out of 4      25%
   Number of DCMs                            1 out of 8      12%
   Number of DSP48A1s                       18 out of 58     31%
   Number of ILOGIC2s                        5 out of 376     1%
   Number of External IOBs                  78 out of 218    35%
      Number of LOCed IOBs                  78 out of 78    100%
   Number of External IOBMs                 11 out of 109    10%
      Number of LOCed IOBMs                 11 out of 11    100%
   Number of External IOBSs                 11 out of 109    10%
      Number of LOCed IOBSs                 11 out of 11    100%
   Number of IODELAY2s                       8 out of 376     2%
   Number of IODRP2_MCBs                    22 out of 376     5%
   Number of ISERDES2s                       8 out of 376     2%
   Number of MCBs                            1 out of 2      50%
   Number of OLOGIC2s                       12 out of 376     3%
   Number of OSERDES2s                      50 out of 376    13%
   Number of PLL_ADVs                        3 out of 4      75%
   Number of RAMB16BWERs                    52 out of 116    44%
   Number of RAMB8BWERs                      5 out of 232     2%
   Number of SLICEXs                      4064 out of 6822   59%
      Number of LOCed SLICEXs                1 out of 4064    1%
   Number of Slice Registers             11875 out of 54576  21%
      Number used as Flip Flops          11863
      Number used as Latches                 5
      Number used as LatchThrus              7
   Number of Slice LUTS                  14334 out of 27288  52%
   Number of Slice LUT-Flip Flop pairs   14792 out of 27288  54%
Overall effort level (-ol):   High
Router effort level (-rl):    High      ...  ERROR:Xflow - Program par returned error code 30. Aborting flow execution...
make: *** [__xps/system_routed] Error 1 Message Edited by thirdeye on 03-24-2010 09:28 AM