PID (FPGA) - Convert 16bit output to 24 bit

Hello,
Im controlling a device in Closed Loop using the PID (FPGA) vi. The output of this is I16, but it would be nice if I could convert it to a I24, or I32. The output of this vi is sent to two different Analog Outs on my Op-Amp circuitry. The op-amps are set up as summing amps, so it would be ideal to send the lower 8 bits to the first AO (fine output), and the top 16 (15+sign) to the second AO (coarse output).
I haven't found an easy way to do this yet. So far, I've been thinking of just using the I16 output value, split it into two 8 bit numbers. The lower 8 bit controls my first AO. The upper 8 bits is combined with another 8 bit register that gets incremented everytime the 8-bit number becomes saturated, and controls the 2nd AO.
I've attached a pic to make it more clear (I hope?). If I should be doing this another way, please let me know.
Or maybe I need to be controlling this system with 2 parrallel PIDs? One controlling the coarse control, the other the fine. The feedback would be the same for both PIDs.

Hi bones,
even on FPGA you should be able to use "split numbers" and "join numbers" functions...
And you can use boolean operators on numbers. Like sign = I16 && 0x8000
That way you would get away from all those number TO boolean array TO cluster of booleans TO unbundle TO bundle TO boolean array TO number conversions (also called RubeGoldberg, search for this in the forum!).
Message Edited by GerdW on 12-07-2009 08:52 PM
Best regards,
GerdW
CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
Kudos are welcome

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Bonjour à tous,
Devant développer une régulation numérique en PID, je m'était inspiré d'un exemple de PID FPGA se trouvant dans LabVIEW pour développer mes programme RT et FPGA que vous trouverez en piece jointe.
Ayant finis la premiere partie de développement pour pouvoir tester le PID simplement sur mon système, je suis passé aux tests.
J'ai commencé par agir sur le coefficient proportionnel pour asservir le procédé, jusque là rien de bien compliqué. Une fois le gain proportionnel fixé, la suite logique est de fixé le gain intégrateur qui est sensé supprimé l'erreur statique qui pourrait resté. Mais là c'est le drame ! Cette partie ne fonctionne pas du tout et fais faire n'importe quoi au systéme.
Je voulais donc savoir si quelqu'un avait réussit a faire fonctionner ce PID et comment il avait fait.
Sinon est-ce que qu'un aurait une idée de comment je pourrais m'y prendre ?
Cordialement
Nathan
Pièces jointes :
PID.zip ‏401 KB

a couple of things. you are specifying 2 usec as loop rate but the module you are using for output is 10 usec.
you are specifying loop rate of 2 usec but your acquisition rate is specified as 20 usec.
the value of the calculated integrator coefficient is likely too small for the 16 bit PID calculation NI uses.
you will be better off coding your own PID algorithm modeled after the NI one.
Stu McFarlane
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Message was edited by: Pierre L.

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Hi,
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Sriprabha

Hi Graham ,
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