PlanAhead - unable to open design - security attributes in generated netlist

Question

Hello,
I am using ISE and PlanAhead 14.3 and the design goes fine inside just the ISE flow,
but does not open in PlanAhead at all when I try to analyze or floor plan the device.
The exact message is:
ERROR: [Designutils 20-396] Could not read top design file *.ngc because ngc2edif command failed wit the following message:
ERROR:NetListWriters - The design contains secured core(s). Creation of the output netlist is prohibited. A license for the secure IP is required from Xilinx.
My third party IP core provider claims that the issue is known in PlanAheadTM 12.4/13.1:
"PlanAhead can only be used pre-synthesis with the EtherCAT IP Core (e.g. for pin planning), because
PlanAhead does not support the security attributes in the generated netlist like ISE. Xilinx is aware of
this issue."
My question is: Is that issue still not solved?
This is a crucial issue for me because I can not easily floorplan or use partitions for my design at the moment.
 

Answer 1

I'm having exactly the same problem (can't floorplan due to secured core).
if I understand this answer record correclty, that workaround will only prevent the warning: it won't solve that PlanAhead doesn't show placement results for secured cores.  This will make it very difficult to verify the floorplanning was successful or any idea of how well its going.  It does not solve the problem.