Problem during the simulation of IP Xilinx EM-DI-40GEMAC-PROJ

Question

Hello,
I'm currently working with the IP Xilinx EM-DI-40GEMAC-PROJ and during a simulation i got a two errors when sending 20000 frames.
The test consist in creating a loopback with two instance of Xilinx EM-DI-40GEMAC-PROJ. I write data on the LBUS interface on the first IP, the data go to the second IP, then go into a FIFO, then the data from the fifo enter the second IP and i read the data on the output port of the LBUS interface in the first IP.
so the data path is the following :
input LBUS IP 1 =>  output serdes IP 1 => input serdes IP 2 => output LBUS IP 2 => input FIFO =>
=> output FIFO => input LBUS IP 2 => output serdes IP 2 => input serdes IP 1 => output LBUS IP 1
the data sends where the same for the 20000 frames, six words of 256 bits and a seven one with only 32 bits.
i check that the data where send as they should be, in compliance with the LBUS protocol.
A new frame was send 100ns after the previous one was send.
when i check for the two errors, i see no problem during the first phase of the test (before the fifo) but during the other, in found two frame with bad FCS status
could you please help me resolve this issue
kind regards
Raphaël Lemaire

Answer 1

 You can ignore them safely if there are no critcal warnings