RE: (HLS) Why does Verilog pointer requires two clocks to get updated??

Question

In HLS (2015.2), I created a simple comparator circuit. The HLS C-simulation worked fine. The HLS C-function compares
8-bit integers received from an 8-bit data bus against a fixed array of 8-bit integers. If the first integer matches, a pointer is incremented, and the C-function will then look for the 2nd integer in the array. If the sequence of 8-bit integers on the data
bus matches the sequence of bytes in the stored array, a  match is detected.
After observing a good C-simulation, I instantiated the HLS Verilog file code into the original manually generated top-level
chip Verilog code, and attempted a Modelsim simulation. It did not work!!
The HLS generated Verilog file has the ports below:
ap_clk
ap_rst
ap_start
ch(7:0)   <---    This is the incoming 8-bit data bus.
ch_valid   <----   This is an input that indicates the ch(7:0) data bus has valid data.
ap_return   <---   This is the match signal.
If ch_valid is HIGH, the comparator compares ch(7:0) data bus against the known internal fixed array of 8-bit integers. The
ch(7:0) data bus changes every ap_clk. The problem with the HLS verilog code is that two clock cycles are needed to update the pointer, which points to the next integer in the fixed array. For the HLS circuit to work properly, the ch(7:0) data bus can't change every clock-cycle. The ch(7:0) data bus needs to be stable for 2-clock cycles. The only reason I found this was
due to the ModelSim simulation. In the C-code below, the fixed array is "pattern0", while the pointer is "check0."
int compare (uint8_t ch, int ch_valid, int sop)
uint8_t pattern0[24] = {0xaa, 0xbb, 0xcc, 0xdd, 0x12, 0x34, 0x56, 0x78, 0x11, 0x11, 0x22, 0x22, \
                                0x33, 0x33, 0x44, 0x44, 0x22, 0x22, 0x33, 0x33, 0x44, 0x44, 0x55, 0x55};
static int prematch0 = 0, check0 = 0, match0 = 0;
int j;
if (ch_valid == 1) {
    if(check0 < sizeof(pattern0)){
         if(ch == pattern0[check0]) {
            prematch0 = 1;
            check0 = check0+1;
         else {
             prematch0 = 0;
             check0 = 0;
     else if ((check0 == sizeof(pattern0)) && (prematch0 == 1)) {
          check0 = check0;
          match0 = 1;
          prematch0 = 1;
     else {
          check0 = check0;
          match0 = match0;
          prematch0 = prematch0;
else {
       check0 = check0;
       match0 = match0;
       prematch0 = prematch0;
return (match0);
If I write this code manually in Verilog, the check0 pointer is updated in one clock cycle.
Questions:
Why does HLS need two clock cycles to update the check0 pointer?
Do I need to set an HLS directive to cause the verilog code to be generated in a different way?
Does the C-code need to be written differently?
Thanks,
Roy

Answer 1

Hi Debraj,
Thanks for the response. I have another question.
I quicly took the C-code above and added a Verilog clock statement.  The code below would execute in one clock.
Is there any way I can re-write the C-code to reduce the 2cc down to 1cc, or is this not possible?
always @(posedge ap_clk) {
   if (ch_valid == 1) {
       if(check0 < sizeof(pattern0)){
            if(ch == pattern0[check0]) {
                prematch0 = 1;
                check0 = check0+1;
            else {
                prematch0 = 0;
                check0 = 0;
       else if ((check0 == sizeof(pattern0)) && (prematch0 == 1)) {
            check0 = check0;
            match0 = 1;
            prematch0 = 1;
       else {
            check0 = check0;
            match0 = match0;
            prematch0 = prematch0;
    else {
       check0 = check0;
       match0 = match0;
       prematch0 = prematch0;
Thanks,
Roy