[RT] Meaning of Timed Loop "reset at structure start"?

Using LabView RT the Timed Loop and also the Simulation Loop have a hardware clock feature called 1 MHz. Each iteration is done in sync with the hardware clock ticks.
But what's the difference between 1 MHz and 1 MHz <reset at structure start>? My guess:
The first option starts the loop with the next hardware clock tick (waiting)
The second option starts the loop immediately (so the loop is running with a "tick offset")
The hardware clock "reset" does not affect other Timed or Simulation Loops running at the same time
Is this correct?

Hi,
in the following link you can find further information about this topic.
http://zone.ni.com/reference/en-XX/help/371361H-01/lvdialog/loop_configuration_db/
I have a VI attached which shows you the difference between these two options in a practical example. Just try out the different options for the timed loop.
Without <reset at structure start> the timed loop wants to catch up a time delay after its first execution, with this option enabled it still works fine for the upcoming
iterations.
Kind Regards
Thomas
Attachments:
TestTimedLoop Folder.zip ‏23 KB

Similar Messages

Event Structure in Timed Loop in real time cannot work

I am a new user for LabVIEW. And I met a problem which really frastre me!!! Hope someone can help me out. Thanks in advance!
I simply want to use event structure under timed loop, which is extrmely important in my design.
However, this works very good in my computer (without connect to FPGA).
Once I connect it to FPGA, then I can run it still but there is no response!
My file is attached. Please somebody helps me!
Looking forward to your answers!
Solved!
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Attachments:
Test for Timed Loop.vi ‏9 KB

The FPGA runs headless. Event structures are not going to work. What you need to do is have an application on your host where the user presses a button, changes a value, etc. That event should send a message via TCP/IP to the code running in the real time environment. Then the real time environment should set a control on the FPGA to the value you want.
In general, real time programming with FPGA has multiple layers.
1) Host code-> handles user interactions and communicates them to real time code via TCP,UDP, etc. Displays data to user sent from the RT controller.
2) Real time code->runs headlessly. Handles messages from Host code, processes FPGA data, communicates with FPGA much like the host code communicates with the real time code
3) FPGA -> does acquistion and passes it via FIFO to the RT
The first thing you need to do is understand the architecture and how all these pieces of the puzzle work together before throwing things down on a diagram.
CLA, LabVIEW Versions 2010-2013

Who know the difference between the two Timed Loop structures in NI's examples named PAC Simulation.vi?

My LabVIEW version is LabVIEW 8.0.
When I look up the help document about Timed Loop, I find two examples about Timed Loop with the same file name and different file path.
One is "labview\examples\general\plat-timedloopframes.llb\PAC Simulation.vi",
and the other is "labview\examples\general\timedloop.llb\PAC Simulation.vi".
The function of these two examples is almost the same. But they display different results when running. I debug them and find that the value of Actual Start [f] of these two timed loop is different. Its value is constand in one vi and increasing in another vi. But the configuration of these two timed loops is the same.
Can anyone tell me the diffrence between these two timed loops?
Thanks!

After I posted this, I realized there was one more "Time" clock, namely the Time node on the Event structure. How is this clock (which I will call ET, for Event Time) related to the Global Start Time (or GST) and the TimeStamp (TS)?
ET represents time in milliseconds, using a U32. The largest value that can be represented is roughly 4 billion, but there are more than 30 billion milliseconds per year. Hence this "clock" cannot directly keep the same time as the GST or TS.
However, on the PC, if you multiply the ET value by a million (thereby converting the time to nanoseconds) and compare this value to GST, you'll see they are basically the same. Thus, on the PC, ET and GST are "in sync", but not in sync with TS.
On a real-time PXI system, we already established that TS and GST are "in sync" -- what about ET? Curiously, this does not seem to be synchronized with anything.
A Word to the Wise -- when I originally added the Event structure, I synchronized it with the Timed Loop using a Value(Signalling) property node, which worked fine on the PC, but failed to fire on the PXI. I'd forgotten that you can't use this trick on real-time systems, as they have no Front Panel objects, hence the implementation using Dynamic Events.
Attachments:
TS GST ET VI.png ‏16 KB

Questions about parallel and series sturcture in SCTL (single clock timed loop) in FPGA VI

I am using LV 8.2.
I have wriiten a FPGA VI, in this VI, there are 3 filters inside the SCTL (single clock timed loop) (I use the shift register to be the effect of unit delay). Would I save the resources of the FPGA used (such as slices and LUT) in the compliation report if I use 3 SCTL ( 1 SCTL contain 1 filter) and cascade them in series?
Thank you!

Sorry, I am afraid that you have misunderstood my meaning.
Here is the method you suggested before:
I mean I use the shift registers attached in the while loop, not in the SCTL. The number of shift registers used will not be decreased when we increase the number of SCTL in the second plate of the flat sequence structure. Totally , there are 6 pairs shift registers for 3 filters (1 filter needs 2 pairs). I mean I put the calculation parts, such as b0*x[n]+b1*x[n-1]+b2*x[n-2] inside the SCTL ( the operations of multiplication and add). Instead of putting 3 filters numeric operation part in one SCTL. will we reduce the resources used if we use 1 SCTL to do the operation parts of 1 filter? As the code inside each SCTL will be reduced.
Maybe you tell me if such approach will reduce the reosources used? Or there is no difference?
Thank you!

Run once inside timed loop

I have a timed loop that monitors equipment. Whenever there is a fault I have it send a notification email. My problem is how to stop it from sending email every single time the time loop is executed. I tried placing the send email inside a for loop but quickly realized that the entire loop itself is reiterted. Any help is much appreiciated.
Solved!
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Hi icemaker
I'm not really sure what you mean. Wouldn't a case structure be a solution?
Could you post some code so we can see what you are doing?
Best Regards
David
NISW
Message Edited by Davidek on 10-02-2009 09:58 AM
Message Edited by Davidek on 10-02-2009 10:00 AM

Is there a way to immediately abort a timed loop

Im writing a program that when completed, could run for a very very long time. But I need a timed loop to execute every 60 secs. The two option I have come up with are these
1. Timed Loop executing every minute
2. Timed Loop executing every second, but processing the contents every minute.
First way means I can't stop the loop until the time expires (more desirable than the 2nd option), the second option relies on the ability to determine when a minute is up based upon a 1Hz iteration rate, but from what I am reading, the iteration counter will eventually get to its max value and just hold its value, while the loop continues to execute (hence I lose my logic for content execution)
I'm really hoping there is a way to do an immediate abort of a Timed Loop, but i'm not finding a way, lol
Solved!
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If you want to use a timed loop, you can stop it at any time using the Stop Timed Structure tool. (even if the conditional terminal is hardwired to never stop!)
For example in the following code draft, pressing the stop button will stop and complete the timed loop immediately, no matter how long the interval is.
(Note: Configure the timed loop to get the current name, or set your own)
LabVIEW Champion . Do more with less code and in less time .
Attachments:
StopTimedStructure.png ‏12 KB

Timed loop inside a flat sequence not terminating

Inside a while loop there is an event structure. Inside that there is a flat sequence. On one of the frames there is a timed loop that quits after so many iterations. The timed loop finishes but the flat sequence doesn't execute the next sequence. What am I not doing right?

First, you have too many local variables. This could be leading to race conditions.
I think you have a couple problems in the use of event structures. It is a bad idea to put any long running code inside an event case. It will prevent the Event Structure from handling any other events in the mean time. You have several timed loops running that in that one sequence frame.
But the bigger problem is the next sequence frame. You have a while loop that only ends once all the queues are empty. Can you guarantee that all the queues get emptied?
You have laid out the code very neatly, but you have used a lot of odd things in there. (Number to boolean array, to cluster, to unbundle the cluster to individual indicators.) Why not just go from Boolean array to and index array function. No need for the intermediate cluster conversion. Why not set up the indicators as an indicator array and just write to them directly.
The code is so much intertwined between when queues are created, filled, emptied, destroyed, events happen... And this is all multiplied by at least 4 times for each camera. And there are 4 major event structures going on. This is a very ambitious project for an inexperience LabVIEW user. You need to step back, get one thing working right, and design so that you can scale the architecture upward. Many of the structures you have essentially duplicated and belong in subVI's.

Restarting counter in Timed Loop

I have a timed loop inside a state machine, used to start/stop a data acquisition sequence.
It works fine, but I'm monitoring the "i" count and Actual End [i-1] values and after the start/stop/start sequence
these values continue to grow and don't get reset to zero. I would expect a While Loop to reset the "i"
variable every time is is called, but I don't see any option for resetting the time looped.
I can get around it, but I would expect a reset method for this loop, so I'm just wondering if I'm missing something.
Maybe I need to use "Create Timing Source" instead of the setting it iin the dialog box?
Labview 2010f1 on Windows Vista SP2 PC

This might help. Here is a part of the png file you posted. I put in "Structure Name>" to point to the Structure Name input. Notice that the name "bob" is listed as the Structure Name. You must be on Win7 which uses different fonts than XP - that's probably why the name is only half visible.
Note that the Clock name is connected to the (timing) Source Name input.
I'm attaching an updated version of the file with the Timing Loop name wired directly.
Thanks for posting your timed loop interations3 program in 2009. When I run this code, the Iteration Count DOES reset when the Timed Loop is restarted.
steve
Help the forum when you get help. Click the "Solution?" icon on the reply that answers your
question. Give "Kudos" to replies that help.
Attachments:
New timed loop interations.vi ‏42 KB

LabVIEW RT, Timed loop, finished late, Call by reference

I have a timed loop triggered by the sample clock of a DAQ-Card. The sample Clock is 8 kHz and the loop will run with dt = 4. Normally the loop is running without finished late[i-1]. But from time to time it happens that the loop is running extremly longer which means instead of 0.5 millisec it needs 4 - 5 millisec. It seems this doesn't never occur while accessing DAQmx.
The application uses plugin technologies and some of the VIs in the timed loop are preloaded and called by Call by Reference.
Does those VIs inherit the priority, execution system and CPU of the timed loop?
The application is running on LV RT 2009 on a Dual core PXI-Controller. The timed loop is bound to CPU 1. There is no difference runinng the application from the development environment or as a startup application.
For the measuring test I modified the application in a way that I don't have:
disk access for storing the result file
TCP/IP communication
Controls on the front panel of the top level VI
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

To keep you informed:
I stripped the application and have left only the measurement storing module and the timed loop. The loop was using the microsecond timer running each 500 µsec. Additional all Non-Real-Time modules were loaded and only one module creates a XML string and sends it to the communication layer which will drop it because no TCP/IP port is open. The creation of the XML string is done each 300 ms.
In this case I don't have any finished late iterations
Next I added the DAQ Module. Now I get finished late again but with a lesser frequency as original.
I removed all unnesseccary tasks from the DAQ moulde leaving one task for a PXI-4204 for using as the clock source for the timed loop. No I get finished late seldom.
I removed the module which will send the XML string and I don't get finished late.
Next I was adding code to see memory allocation. I can when memory allocation is changing but it is not related to the finished late iterations.
Next time I have the chance to do more tests I will see which DAQ task triggers the finished late iterations. I have one AI task on a PXI-4204, 4 Counter tasks on a PXI-6602, 1 DI task on a PXI-6514, 1 DO task on a PXI-6514, 1 DI task on a PXI-6259, 1 DO task on a PXI-6259, 1 AO task on a PXI-6259 and 1 AO task on a PXI-6711.
The AI task on the PXI-4204 is running in Continous Sampling (Single Point HW Timed is not supported), all other tasks exept the DI and DO are Single Point HW Timed.
Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

Using timer/counter with PCI-6221/USB-6210 to control timed-loop VI

Dear all,
I need to ask about two devices and one of their functionalities, PCI-6221 and USB-6210. For our NI-based system, we need to control some timings in a Timed-Loop vi, for that currently we are using PCI-6221 and we give external TTL signal (at 1 kHz) to it,
recenntly we need to make some changes and for that we found USB 6210 DAQ to be more suitable, but we need to clear ourselves on some specific things.
Can the counter/timers functions available in the either PCI 6221 or USB 6210 can be used to control the Timed-loop VI by giving external clock or by using their own internal clock source?
Although we are using external clock with the PCI 6221 but we want to know about the usage of their internal clock, also are controlling timed-loop also possible for USB-6210
Also... What if we use the RTOS, are they still able to control the timed-loop VI without giving any 'EXTERNAL CLOCK' and using the internal clock sources of the DAQs
Waiting for reply,
Bests,
RaJaf
Solved!
Go to Solution.

Ben,
I having read previous email which I send earlier with general overview, we discussed in more detail within our team and I am giviing the specific answers.
Please check in RED the most recent answers. Blue are the questions/suggestions by your side.
1.    Using Internal hardware clock of PCI-6221 would enable us get rid of external clock, but how to divert the internal hardware clock to the current settings. Any idea (can you provide us with some reference manul for otherwise). I mean is there some flag-bit etc. or VI
2.       Is it also meant that with the installation of RTOS the timed-loop can directly get the timing source from the internal hardware clock PCI-6221? --- How???
3.       In order to make desktop to work as RT system, what is the hardware (motherboard, processor, etc..) requirement? What are the LabVIEW modules (specific name) that needed to be installed? Our platform is LabVIEW 8.6. (Currently we have windows-7 with i7 core processor)
What kind of application are you intending for this system? ---- high-speed laser scanning system.
Are you most concerned about accuracy, speed, or responsiveness? To control the laser mirror scanner to move at 1 kHz or 2 kHz speed. On the other hands, using PCI-5105 (128 MB memory) as a DAQ for real-time/on-the-fly data processing.
Bests,
RAJAF

Unable to run Timed Loops

Bit of an odd one that had me scratching my head.
I have a development system consisting of a PC running a 7842R, acquiring analogue and digital data from the FPGA, loading it into a shared variable, and reading it out within a timed loop on the host as one parallel loop in a producer-consumer architecture.
All's well until one day last week when I noticed my host VI becoming unresponsive.
After a bit of digging, I find that the timed loop doesn't run at all. Replacing with a while loop with a wait at least allows me to show that the error is timed loop related, but it's not a viable long term option for me. Creating a new project and a new VI with a simple timed loop showed the same behaviour.
A restart of the system, and rerunning the same VIs, and no problems since.
So, questions:
1) Has anyone else seen this behaviour?
2) Any idea what causes it? A service crashing, for example?
3) Is there a way of recovering without a reboot? If it's a service crash, I'm hopeful.
The system will eventually form part of a production test environment, hence the query.
Edit - also, wiring error terminals of a timed loop is a good way of highlighting errors of course.
FWIW, LV2012 SP1 32bit, Win7 64bit, Core2 Duo, 4GB RAM, tassels from the handlebars etc.
CLD

The timed loop is used to read all elements from a DMA FIFO and load them into a buffer FGV, which spits out packets of N samples long once they've assembled within the FGV. Ordinarily, I'd do this with a timed while loop and be perfectly happy to do so. However, the elements are actually an interleaved array, meaning that I have to demux them in the correct order that they were loaded.
I use timed loops for a number of reasons: on my current Windows host, I've found that using a while loop has caused me more problems with respect to disordered packets, and that at least with using multiple timed loops (two, at most), I can assign priority to the acquire loop. Finally, it's also a development platform, and will be deployed onto an sbRIO once the electronics integration is finished in a week or two!
W.r.t. system resources, there's very little else running on that system, but that doesn't normally stop Windows
I recognise it's not ideal to run a software timed loop under Windows, but when you cannot run a blank project with Optimizing timed loop rate.vi from the shipped examples with nothing else running, it makes me curious to know why!
CLD

Memory leak in Real-Time caused by VISA Read and Timed Loop data nodes? Doesn't make sense.

Working with LV 8.2.1 real-time to develop a host of applications that monitor or emulate computers on RS-422 busses. The following screen shots were taken from an application that monitors a 200Hz transmission. After a few hours, the PXI station would crash with an awesome array of angry messages...most implying something about a loss of memory. After much hair pulling and passing of the buck, my associate was able to discover while watching the available memory on the controller that memory loss was occurring with every loop containing a VISA read and error propogation using the data nodes (see Memory Leak.jpg). He found that if he switched the error propogation to regular old-fashioned shift registers, then the available memory was rock-solid. (a la No Memory Leak.jpg)
Any ideas what could be causing this? Do you see any problems with the way we code these sorts of loops? We are always attempting to optimize the way we use memory on our time-critical applications and VISA reads and DAQmx Reads give us the most heartache as we are never able to preallocate memory for these VIs. Any tips?
Dan Marlow
GDLS
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Go to Solution.
Attachments:
Memory Leak.JPG ‏136 KB
No Memory Leak.JPG ‏137 KB

Hi thisisnotadream,
This problem has been reported, and you seem to be exactly reproducing the conditions required to see this problem. This was reported to R&D (# 134314) for further investigation. There are multiple possible workarounds, one of which is the one that you have already found of wiring the error directly into the loop. Other situations that result in no memory leak are:
1. If the bytes at port property node is not there and a read just happens in every iteration and resulting timeouts are ignored.
2. If the case structure is gone and just blindly check the bytes at port and read every iteration.
3. If the Timed Loop is turned into a While loop.
Thanks for the feedback!
Regards,Stephen S.
National Instruments
Applications Engineering

How to pause and restart a timed loop in Labview

I am trying to pause and then restart a timed process (series of stepd that happen at precise times), which is implemented using a timed loop.
I was wondering if anybody out there can give me a hint.
Thanks

Roxanne,
Well, it's not exactly a "pause", but here's a way to stop and re-start your Timed Loop.
See the attached example in LV2010.
A While Loop and a Queue are used to allow you to start and re-start the Timed Loop.
The "Stop Timed Structure" vi is used to stop the Timed Loop.
Releasing the Queue stops the While Loop when you end the program.
Note that the example is very similar to the NI template "Producer/Consumer Design Pattern (Events)". (File>>New)
steve
Help the forum when you get help. Click the "Solution?" icon on the reply that answers your
question. Give "Kudos" to replies that help.
Attachments:
timed loop.vi ‏39 KB

Timed loop not starting - works after closing and opening project

Refer the image below - a simple timed loop should run when the Run button is pressed. What happens is that the parallel vi runs (see arrow) but the vi inside the loop doesn't. Both vi's shown run forever (i.e. the timed loop is only used to specify the CPU).
When I press the Abort Execution button, strangely it can then be seen that the execution highlighting runs into and through the timed loop and probe 50 is updated.
This sorted itself out after I closed the project and opened it again so its not a critical issue - was simply wondering what could cause this?

That program looks kinda weird.
First of all, avoid to use flat sequence structures whenever you can, or use it only when you are going to initialize something, or when your program has an specific sequence.
I think you have a problem the way you are conecting the subvis. Remember that in LabVIEW, the flow of the data will determine the order of execution, and in your case, the conections looks kinda weird.
I have a question; Do the subvis need to run simultainously?, or what do you need to do exactly

Does two timed loop work together? is it possible....

Hello
I use Crio in scan mode and have problem with timed loop. I use two timed loop for two different PID loop. I need to get 1ms delay for PID loop. But When I two run realtime side with timed loop, only one of them work (when ı send command from host side). Is it possible to run two time loop 1ms. How can I configure each timed loop work together properly? (ı configured the each time loop as synchron scan enginee 1ms)
Both array are used for sinusoidal position data form host vi. I use time delay (1 ms) to make certain frequency with sample size(I adjust sample size for 1000 for 1 hz 500 for 2 hz).Each loop control to position of servo system with PID. So I use two VI in my host side and I send two different sinus data with array. I tested with one timed loop it works vey well. But When I try it two time loop it dosent work.
Attachments:
RT TEK.vi ‏105 KB

Two loops in parallell is quite easy, you just need two unconnected loops. If there's a wire in between you get data dependency which means the 2nd loop will wait until the 1st one finishes.
Is that what happening to you? (I cant open the file)
/Y
LabVIEW 8.2 - 2014
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[RT] Meaning of Timed Loop "reset at structure start"?

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