Spartan 6 LX100 - synthesys OK but Place:543 error when mapping

Question

Hi all,
I am currently working on a code for a Spartan 6 LX100 and I have about 70% of the code ready. I have decided to implement the design half-way to avoid any surprises at the end and well, it didn't fit.
When I synthesyze the design it appears to have quite some space left to map:
Slice Logic Utilization:
Number of Slice Registers: 9353 out of 126576 7%
Number of Slice LUTs: 10582 out of 63288 16%
Number used as Logic: 10581 out of 63288 16%
Number used as Memory: 1 out of 15616 0%
Number used as SRL: 1
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 12463
Number with an unused Flip Flop: 3110 out of 12463 24%
Number with an unused LUT: 1881 out of 12463 15%
Number of fully used LUT-FF pairs: 7472 out of 12463 59%
Number of unique control sets: 457
IO Utilization:
Number of IOs: 108
Number of bonded IOBs: 101 out of 326 30%
IOB Flip Flops/Latches: 61
Specific Feature Utilization:
Number of Block RAM/FIFO: 153 out of 268 57%
Number using Block RAM only: 153
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
Number of DSP48A1s: 8 out of 180 4%
The percentage of fully used LUT-FF is of 59%, which I reckon is a good number (might be wrong) and means I am not having trouble with too many control sets.
Then I tried to implement the design and it took me about 20 hours and fails at the end.
Place:543 - This design does not fit into the number of slices available in this device due to the complexity of the design and/or constraints.
Unplaced instances by type:
BLOCKRAM 100 (97.1)
The following instances are the last set of instances that failed to place:
0. BLOCKRAM
i_AVERAGE_DATA/i_AVG_VALID_COLOUR4_RE_CHT4/U0/xst_blk_mem_generator/gnativebm
g.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SDP.SIMPLE_PRIM9
.ram
1. BLOCKRAM etc...
These instances could be impacted by the following constraints
(the line IDs below correspond with the instances above):
Clock Region restrictions
0.
CLOCKREGION_X0Y0, CLOCKREGION_X1Y0
1.
CLOCKREGION_X0Y0, CLOCKREGION_X1Y0
etc...
I can't understand why I am getting this error, it seems like the tool can't route the clock nets to the BRAMs, but why? It can't really figure it out by the information the report is giving me.
By the way, the only reason I am using an LX100 is because I need 266 (18K) BRAMs for this design.
Thanks a lot for the help.
Best regards,
croto

Answer 1

This is the configuration file (.xco) from Core Generator. I can't see any obvious problems:
# Xilinx Core Generator version 14.7
# Date: Mon Jul 27 15:17:52 2015
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx100
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=NONE
CSET component_name=BRAM_SDP_1Kx9
CSET disable_collision_warnings=true
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_32bit_address=false
CSET enable_a=Use_ENA_Pin
CSET enable_b=Use_ENB_Pin
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=true
CSET interface_type=Native
CSET load_init_file=false
CSET mem_file=no_Mem_file_loaded
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=9
CSET read_width_b=9
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_bram_block=Stand_Alone
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=1024
CSET write_width_a=9
CSET write_width_b=9
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T16:22:25Z
# END Extra information
GENERATE
# CRC: f38a1908