Synchronize two counter outputs on 6071E card

Well, it's the usual how do I synchronize two counters problem.
I'm using the 6071E with DAQmx .NET 4.0. I define a Task and attach to it two counter output channels with implicit timing and zero initial delay . When running the program
I catch the first edge with a scope single trigger. There is always a delay between the first edge of ctr0 and the first edge of ctr1 of 16.3 microsecs. Is there a way, besides setting the initial delay of ctr0 to 16.3 microsecs, to make the counters to always start together? what is the source of the delay(software/hardware) and should it always stay constant.
any help is welcome
Solved!
Go to Solution.

The source of the delay is that despite being in the same tasks the counters are still started sequentially by software.  I'm surprised the delay you are seeing is constant.
If you want the counters to start together you should configure a start trigger.  Once you start the counter tasks in software, issue the start trigger to begin generating your output pulses.  The start trigger must be a hardware signal--as an example you might configure a software-timed digital output and wire it back in to one of the PFI lines.
If you want to avoid any additional wiring, you could split the counters into two separate tasks.  Trigger one counter with the internal output of the other (start the task that is going to be triggered first).  Doing this instead of using an external trigger, I would expect an additional delay between the counters on the order of 100 ns as the initial delay is at minimum 2 timebase ticks.
Best Regards,
John Passiak

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    To summarize:
    Steps Taken:
    1. Test Path 1 = SUCCESS
    2. Test Path 2 = SUCCESS
    3. Test Path 3 = Erratic Frequency (Two Frequencies repeated over and over again in my frequency results array)
    4. Test Path 4 = Erratic Frequency (Two Frequencies repeated over and over again in my frequency results array)
    5. Reset the PXI 6229 Card
    6. Test Path 3 = SUCCESS
    7. Test Path 4 = SUCCESS
    8. Test Path 3 = Erratic Frequency (Two Frequencies repeated over and over again in my frequency results array)
    9. Test Path 4 = Erratic Frequency (Two Frequencies repeated over and over again in my frequency results array)
    I am wondering if Port 2 (P2.0-P2.7) on the 6229 card has certain dependecies and this is why I am seeing issues.  I am trying to get around this issue so that I don't have to always reset the card.
    Are P2.0-P2.3 (PFI8-PFI11) and P2.4-P2.7 (PFI12-PFI15) treated differently or require different setup?  How do I resolve this issue?
    Thanks so much!

    I have a theory...
    The DAQ card follows a policy called "lazy uncommit" wherein the terminal used for the output will continue to be connected to the counter even after the task has completed (until the terminal is needed for something else).  So as you run more tests, the counter output will end up driving more lines.  This behavior should be easy enough to confirm.
    As the DAQ card drives more lines, I'd imagine this affects the actual signal.  You could scope it to check, but it sounds like either the rise/fall times are becoming longer or some extra noise is being introduced on the line.  
    The readings are two different frequencies repeated over and over again and none of those frequencies are the expected frequency which was generated out of the "Counter Output."
    This implies you are picking up an extra edge during transitions--this isn't too uncommon if the signal is noisy since there is no built-in hysteresis on the DAQ card.  I would expect the measured frequencies to have periods that sum to either the full period or the semi-period of your actual signal (depending on how many duplicate edges are detected).
    Suggestions are as follows:
    To stop the DAQ card from driving multiple PFI lines, it would probably be easiest to just programmatically reset the device in between your tests (using DAQmx Reset Device).  If you can't reset the device (e.g. because you are running some other task that can't be interrupted) then you can instead configure a dummy task that uses the PFI line in question as an input.
    To stop the DAQ card from picking up multiple edges during transitions, you should configure a digital filter on the input terminals.  If you reset the device it sounds like this might not be necessary... it's up to you if you want to configure this or not.
    Best Regards,
    John Passiak

  • How to filter starttrigger on counter output precisely

    HW PCI6602
    Measurement studio 2008 (C#)NI-DAQmx 9.02I’m trying to trig a camera using the output from a counter.
    The camera should be trigged when the counter input pulse width is larger than approx (filterPulseWidth 10us).To do this a have set up the following tasktask.COChannels.CreatePulseChannelTime(counter,                "TriggerTaskChannel", COPulseTimeUnits.Seconds, COPulseIdleState.Low, 0, 80E-6, 0.007);             task.Triggers.StartTrigger.Type = StartTriggerType.DigitalEdge;            task.Triggers.StartTrigger.DigitalEdge.Edge = DigitalEdgeStartTriggerEdge.Rising;             task.Triggers.StartTrigger.Retriggerable = true;task.Triggers.StartTrigger.DigitalEdge.DigitalFilterMinimumPulseWidth = filterPulseWidth;            task.Triggers.StartTrigger.DigitalEdge.DigitalFilterEnable = true;Unfortunatly this filter has the following behaviour”If the period of the filter clock timebase is tfltrclk, this filter guarantees topass pulse widths that are 2*tfltrclk or longer and to block pulse widths thatare tfltrclk or shorter. A pulse with a width between these two ranges may ormay not pass, depending on the phase of the pulse with respect to the filterclock timebase”.It means that I have no sharp distinction on my filter as one would when applying a filter to an ordinary pulse width measuring task. Implementing this with via the software in a callback is to slow.The bottom line is that I would like to generate a pulse on my counter output when the trigger/counter input is greater than say 10us. The output pulse could be predetermind as in the sample code above or as long as the filtered input (I.e counter just pass filtered input to my output).How can this be done? BR
    Jongas
    Solved!
    Go to Solution.

    Hi Jongas,
    Is it OK if the trigger is sent once the pulse hits 10 us, rather than
    on the exact falling edge?  I'll assume the exact timing isn't as important, but you would like the trigger to occur very close to the falling edge (within a couple of us).  The important thing is that we trigger as close as possible to when the PWM has hit 50% duty cycle.
    Some brainstorming:
    Digital Filtering on the 660x Isn't the Best for This:
    Digital filtering might not be as practical here on your 6602 due to the region of uncertainty between 5 and 10 (or 10 and 20) us pulses.  The TIO boards count two consecutive edges of a filter clock to determine when to pass a signal through so the guaranteed rejected pulse width is always half of your guaranteed passed pulse width (providing an external filter clock timebase that is synchronized with your external signal could potentially reduce this uncertainty but I honestly haven't tried this before and I would imagine it is not going to be very straightforward).
    X Series Alternative:
    Our X Series devices use a different method of digital filtering that would work better for you.  If a hardware change is an option (and you can use PCIe) then you might consider this.  You could use the 20 MHz timebase as your filter clock timebase and could guarantee to pass 10 us (200/20M) and reject 9.95 us (201/20M).  The 6320 is currently our lowest cost X Series board.  A couple of points about this solution:
    1.  To configure the PFI filter, you need to use some sort of dummy task to
    access the property nodes.  Here is an
    example of this (although it is written in LabVIEW).
    2.  You can route the filtered PFI signal to be exported on another PFI line, but this will reserve Counter 3.  This is documented in the Device Routes tab of Measurement and Automation Explorer.
    3.  The filtered output will be 9.95-10 us delayed from the input signal, so you could trigger the camera off of the rising edge of the filtered output directly and be fairly close to the actual falling edge.
    External AND Gate Alternative:
    You could configure a Counter Output to generate a re-triggerable pulse with a 10 us initial delay (to be triggered off of the rising edge of your PWM signal).  Assuming the pulse is short enough to complete before the next period of your PWM signal, the counter output would only be high at the same time as the PWM signal if the signal was longer than 10 us.  Use the external AND gate to combine these two signals and the result would be the trigger for your camera (the rising edge would correspond to 10 us after the PWM signal first goes high).
    If you wanted to you could make the counter output pulse a little longer (say 8 us) and trigger the camera off of the falling edge out of the AND gate (a.k.a. rising edge out of a NAND gate) which would line up with the exact falling edge of the PWM signal.  Don't make the CO pulse too long or it will overlap with the next period of the PWM.
    Another Idea:
    One idea that I keep coming back to is to use the internal rollover event of a counter input task (a pulse is generated whenever a counter rolls over on its Internal Output which can be routed to a PFI line).  I don't think this will work, but the idea in theory would be to:
    1.  Set Default state to known value (e.g. 2^32-200).
    2.  Gate the Counter so it only counts during the time PWM is high.  Have it count the 20 MHz timebase.
    3.  Reset the Counter to default state on the falling edge of the PWM signal.
    4.  The counter would rollover if 200 pulses occurred of the 20 MHz timebase (10 us), and the Counter Output could be routed to a PFI line to trigger the camera.
    The problem is that there is no good way to reset the counter except for an encoder measurement (Kevin has already made a nice suggestion about this).  A Pulse Width Measurement would technically reset the counter, but you cannot currently set the default value of a Pulse Width Measurement task so there is no way to make the rollover happen prematurely).
    Configuring an encoder measurement and working with the multiple counters on the 6602 to produce appropriate A,B, and Z signals might be a method to look into further, but at this point I think you'd be better off with an external AND gate.
    I don't want to say it's impossible with just the 6602, but I can't think of a straightforward way to go about it without external hardware (although maybe I can sleep on it and think of something later... how many counters do you have to work with?). 
    With your current NI Hardware, I think your best bet is to go with an external AND gate.  If you're planning on purchasing an X Series card the digital filtering idea is actually not a bad way to go.
    I hope this is helpful!
    Best Regards,
    John Passiak

  • How to synchronize two fpga DIO?

    Hi!
    I am using two FPGA 7962R (flexrio) with each 6581 terminal board in PXIe-1082 chassis. My problem is how to synchronize two 7962R digital output with PXIe-1082 chassis backplane signal Dstar* or Clk10 or DAQ signal.
    Actually I tried the synchronization with one DAQ counter clock (confering 'Gen Dig Pulse Train-Finite_NI. vi') , and get the signal PXI-Trig0 by source terminal and target terminal connection, but that one does not work properly. Especially, one trigger signal in HOST to set the starting point of each FPGA (7962R), make error by depending on the trigger signal value(Hz value and Timed loop clock in FPGA vi). It was very tricky and not reliable. (I am attaching figure files as explaining the situation)
    My aim is simply to use two FPGA 7962R Digital output as one FPGA, for controling X-axis, Y-axis with each FPGA, while able to change each FPGA (X-axis, Y axis) digital output value. Because the synchronization is not correct, X,Y axis control with Two FPGA currently is out of target if I use simply while-loop design in HOST and timed-loop design in FPGA vi. What is correct design to synchronize the two FPGA 7962R without using PFI line, only with PXIe-1082 chassis backplane signal and able to change the digital output value? Please let me know any idea for HOST vi, FPGA vi programming.
    Many Thanks
    Attachments:
    host1.png ‏47 KB
    fpga1.png ‏131 KB

    Posted response to this in the following thread:
    http://forums.ni.com/t5/Real-Time-Measurement-and/synchronization-two-fpga-7962r-digital-output/m-p/...
    Patrick H | National Instruments | Software Engineer

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