Synchronous IO best practice

Question

I'm writing a simple interface to drive a fairly slow (~25MHz) SPI bus, and have a few questions about best practice.
The FPGA is the master device, which outputs a clock at something like 25MHz. On each rising clock edge, it drives data onto an output pin and latches data from an input pin. A trivial Verilog module would look something like this:
module main (
input clk, // 25MHz FPGA clock
// SPI pins
output spi_clk,
output reg spi_MOSI,
input spi_MISO );
// Generate SPI clock output
ODDR spi_clk_gen (
.Q(spi_clk),
.C(clk),
.CE(1'b1),
.S(1'b0),
.R(1'b0)
.D1(1'b1),
.D2(1'b0) );
reg data_out; // Data we want to drive onto the bus
reg data_in; // Data read from the bus
always @ (posedge clk) spi_MOSI <= data_out;
always @ (posedge clk) data_in <= spi_MISO;
endmodule
To ensure that this meets timing, I add the following constraints to my xdc file
create_generated_clock -name clk_spi -souce [get_pins spi_clk_gen/C] -dvide_by 1 [get_ports clk]
set_porperty IOB FORCE [get_ports {spi_MOSI spi_MISO}]
set_output_delay -clock [get_clocks clk_spi] -max t1 [get_ports spi_MOSI]
set_output_delay -clock [get_clocks clk_spi] -min t2 [get_ports spi_MOSI]
set_input_delay -clock [get_clocks clk_spi] -max t3 [get_ports spi_MISO]
set_input_delay -clock [get_clocks clk_spi] -min t4 [get_ports spi_MISO]
Where:
 - t1 is the SPI slave IC's minimum required setup time + the trace delay (from FPGA output pin to IC input pin) between spi_MOSI and spi_clk, defined in the sense that positive delay => spi_MOSI takes longer to reach the IC than spi_sclk.
 - t2 is the min trace delay - the SPI slave IC's minimum hold time
 - t3 is the sum of the max values of: the trace delay for spi_clk to reach the IC; the trace delay for spi_MISO to reach the FPGA; and, the IC's clk-output delay.
 -t4 same as 53, but sum of min values
My questions are:
1) From the constraints guide UG903, I take it that:
    (A) The reference point for the generated clock, clk_spi, is the output port of the ODDR block (not the FPGA output pin)
    (B) The set_output_delay/set_input_delay constraints relate the time the signal leaves/reaches the FPGA pin to the clock reference point.
So, this constraint doesn't take into account the delay between the ODDR output and the FPGA pin (e.g. the OBUF). Is that correct? Presumably, this delay is small (how small?) so I can comfortably ignore it given the relatively low clock speed I'm operating at. But, if I had brought the clock out through the FPGA fabric instead of using an ODDR (e.g. assign spi_clk = clk) this delay could be pretty large (again, how large typically for a 7-series FPGA?)?
2) I've seen adding the IOB FORCE constraint recommended in a few places. What is the point of this constraint? Presumably, keeping all the IO FFs in IOBs makes the timing very reproducible from build to build, but if the IO timings are all constrained isn't it better to let Vivado decide where to put them?
Thanks for your help!

Answer 1

Hi 
1. Look at the timing report.
2. Yes, if the design was properly constraint, you can leave for Vivado to decide. By default, Vivado also places these IO FFs into IOBs since Vivado placement and routing algorithms tries to meet timing.
Thanks,
Vinay