The precision of the timing analysis

In my project, I can get the timing analysis of the path "clk50M_PE2_ref to FPGA_TEST6". The "clk50M_PE2_ref" and "FPGA_TEST6" are the ports of FPGA. The path delay is 7.473ns from the timing analysis reports.
But when I measure these two ports signal with Oscilloscope, I get the delay time is 5.2ns. The testpoints are at the through-hole on the back of the FPGA (that is the bottom of the PCB).
Why the delay time is different between timing analysis and oscilloscope measurement? Which is the correct in fact?

yssy2000 wrote:
Thanks for your reply!
If I want to know the delay time from A ports to B ports, how to get the exactly value except with the oscilloscope?
That's like asking "how can I get the exact temperature at 2PM tomorrow except by waiting until then and using a thermometer?"
The tools can only predict the delay as a range, minimum to maximum, based on characterization data for your part. There are differences in delay from part to part (Process, the "P" in PVT), with variation in supply voltage (Voltage, the "V" in PVT) and with die temperature (Temperature, the "T" in PVT). You can use a scope or other measuring instrument to find the actual delay for a particular part at a particular voltage and temperature. Even so this delay may change for the same part and voltage supply due to changes in temperature. So the bottom line is, why do you need to know the exact delay? Typically you'd only need to know if you are using the FPGA as a timing generator, and in that case you would need to have a way of calibrating your output delay in order for it to be reliably repeatable.

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I am using labVIEW FPGA 2011 and FlexRIO 7965R (virtex 5 SX95T). I am trying to use multiple simple dual port RAMs (generated through xilinx coregen tool) in cascade. The data read from one memory block is written to the next memory block and so on. I want the design to run as fast as possible. I have used SCTL rate of 346MHz in my design. But when i compile the code, timing violation error occurs. And the maximum clock rate achieved is 291.25MHz. The timing vilation analysis window always show the feedback node and controller as paths which failed to meet the timing contraints. I have also used DMA and VI Scoped FIFOs in my design for data input and output.
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Attachments:
Projec_Memory Block.zip ‏309 KB
Block Memory Generator_GUI.zip ‏236 KB

Have you taken a look around the forums?
http://forums.ni.com/t5/LabVIEW/Compile-Error-in-FlexRIO-FPGA-when-using-derived-clock/td-p/1617226
What is the exact timing violation error you receive? Depending on how your feedback nodes are used it can slow down the clock rate from the desired clock rate. This is what I normally use as a reference for making my code operate more quickly:
http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/registers/#Register_Timing
http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpga/fpga_timed_loop/
http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_pipelining/

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Go to Solution.

Hi CracKatoA.
Take a look at the link bellow:
http://forums.ni.com/ni/board/message?board.id=170&message.id=255126&requireLogin=False
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CASE WHEN T0.[OnHand] = 0 THEN T1.[Price]-T0.[LastPurPrc] ELSE CASE WHEN T0.[OnHand] > 0 THEN T1.[Price]-T0.[StockValue]/T0.[OnHand] END END AS [Margin],
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SUM(IsNull(T1.GrssProfit,0)) 'Gross Profit',
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Message was edited by:
        Ram R

Thanks Sridhar,
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NI PXIe-8108 Embedded controller
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Attachments:
xilinxlogc.txt ‏2313 KB

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