Top level clock timing error 0.00 ns

Question

I am working with Ni 9146 chassis in FPGA.  When the top-level clock was set to default (40 MHz) and the VI was compiled with Xilinx a timing error comes back which states the the time that the code took would be ~0.05 ns, but the expected time was 0.00ns.  Since it was 40 MHz the time required should have been 25ns.  I had the work around that I created a derived clock of 40 MHz, and this makes the compiler think the code needs to run in less than 25ns.  
I do need to know why the default clock does not work though.  
Thank you for your time
Mitchell

Answer 1

I have received similar errors in a few of my projects, typically in the past I have simply changed the "Implementation Strategy" from "default" to "reduced compile time". Although I just received the same error 3 times consecutively now and I'm not sure why. I have the exact same VI implemented on another FPGA of the same type which compiles without problem.
I have received two 50pS timing violations and one 980pS timing violation.
Attached are the screen shots of the two most recent errors. Any insight as to the cause?
I just changed the "Implementation Strategy" to "optimize performance" hopefully this rectifies the issue.
Attachments:
5pS.jpg ‏201 KB
98pS.jpg ‏224 KB