Vivado 2015.1 Bug Report: Adding Required Port without Default Value in Custom Interface Definition

When adding a port using the Custom Interface Definition window and not defining a Default Value, the attached error message appears.  Not only are the html tags visible, but this error should not be thrown in the first place if both Master/Slave Presense is set to "required".  As it is, a port can only be added if a Default Value is given, but can be removed later from the ports table.

yes,I have successfully install petalinux2015.2,but,the issue still be the same as before,the axi 16550 is not working,when I run echo 123 > /dev/ttyS1,my ttyPS0 stop working and axi com keeping null output...
then,I try petalinux2014.4+petalinux2014.4,the difference is the ttyPS0 still alive but axi-com still null...
I found that pl.dtsi file is quite different between the three mode:
M1,petalinux2014.4+vivado2015.1
M2,petalinux2015.2+vivado2015.1
M3,petalinux2014.4+vivado2014.4
most confuse for me is the interrupt ID,
in vivado I connect the axi intterrupt to ID 62 but I get different auto generate dts file
M1:nothing about interrupt and i add manuually in system-top.file
M2:vivado ID is 61 but dts "interrupts = <0 30 4>"
M3:vivado ID is 62 but dts "interrupts = <0 31 4>"
does petalinux auto detect the vivado interrupt connection and ID and write to dts file right or User have to verify and rewrite in ststem-top.dts?
working hard for the issue and hope for a axi demo including petalinux + vivado ,help please

Similar Messages

  • Bug report: adding -fast to thecompilation

    Hi all.
    Compiling the following piece of code on a Sun v60x, I ran across a bug with -fast:
    PROGRAM SMOOTH
    IMPLICIT NONE
    INTEGER, PARAMETER :: i0=100, j0=100, m0=19
    INTEGER :: i, j
    REAL, DIMENSION(i0,j0) :: rho
    INTEGER, DIMENSION(i0,j0) :: imask
    LOGICAL, DIMENSION(i0,j0) :: lmask
    c sumi1, sumi2, sumi3, sumi4, sumi5 use an integer mask to compute sums
    c suml1, suml2, suml2 use a logical mast to compute sums.
    REAL, DIMENSION(i0) :: sumi1, sumi2, sumi3, suml1, suml2, suml3,
    $ sumi4, sumi5
    c set up a checkboard pattern of 1 and 0, or T and F.
    imask(1:i0:2,1:j0:2)=1
    imask(2:i0:2,1:j0:2)=0
    imask(1:i0:2,2:j0:2)=0
    imask(2:i0:2,2:j0:2)=1
    lmask(1:i0:2,1:j0:2)=.true.
    lmask(2:i0:2,1:j0:2)=.false.
    lmask(1:i0:2,2:j0:2)=.false.
    lmask(2:i0:2,2:j0:2)=.true.
    rho = 10.0
    print *,'m0=', m0
    suml1(: )= SUM(rho(1:m0+1,: ),DIM=1, MASK=lmask(1:m0+1,: ))
    sumi1(: )= SUM(rho(1:m0+1,: ),DIM=1, MASK=imask(1:m0+1,: ).eq.1)
    sumi5(: )=SUM(rho(1:m0+1,: )*imask(1:m0+1,: ), DIM=1)
    DO j=1,j0
    sumi2(j)= SUM(rho(1:m0+1,j), MASK=imask(1:m0+1,j).EQ.1)
    ENDDO
    do j=1,j0
    suml2(j)= SUM(rho(1:m0+1,j), MASK=lmask(1:m0+1,j))
    enddo
    do j=1,j0
    sumi4(j)= SUM(rho(1:m0+1,j)*imask(1:m0+1,j))
    enddo
    suml3=0.0
    do j = 1, j0
    DO i=1,m0+1
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    ENDDO
    sumi3=0.0
    DO j=1,j0
    do i = 1, m0+1
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    ENDDO
    DO j = 1, j0
    print *,'j=', j,sumi1(j), sumi2(j), sumi3(j), sumi4(j),sumi5(j)
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    enddo
    print *,lmask(:,j0)
    print *,imask(:,j0)
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    The above program calculates the sum of part of array, not including elements of the array excluded by either an integer mask (imask), or a logical mask (lmask). Each sum calculation (e.g. sumi1) should give identical results - each element of a particular line in the print statement of the final DO loop should report the same result. The purpose of this code is to test various techniques against one another for speed comparisons in a code analyzer. Without the -fast compiler switch the results are as expected:
    f90 -V -g subavsun.F -o subavf90: Sun Fortran 95 8.0 2004/07/15
    fpp: Sun Fortran Utils 5.4 2004/07/15
    f90comp: Sun Fortran 95 8.0 2004/07/15
    f90comp: 88 SOURCE LINES
    f90comp: 0 ERRORS, 0 WARNINGS, 0 OTHER MESSAGES, 0 ANSI
    ld: Software Generation Utilities - Solaris Link Editors: 5.9-1.382
    uname -aSunOS 5.9 Generic_117172-07 i86pc i386 i86pc
    partial sample of results:
    m0= 19
    j= 1 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0
    j= 2 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0
    j= 3 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0
    j= 4 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0
    now add the -fast option:
    f90 -V -fast -g subavsun.F -o subavf90: Sun Fortran 95 8.0 2004/07/15
    fpp: Sun Fortran Utils 5.4 2004/07/15
    f90comp: Sun Fortran 95 8.0 2004/07/15
    f90comp: 88 SOURCE LINES
    f90comp: 0 ERRORS, 0 WARNINGS, 0 OTHER MESSAGES, 0 ANSI
    ir2hf: Sun Compiler Common 9.0 2004/07/15
    ube_ipa: Sun Compiler Common 9.0 2004/07/15
    ube: Sun Compiler Common 9.0 2004/07/15
    ld: Software Generation Utilities - Solaris Link Editors: 5.9-1.382
    and I get:
    m0= 19
    j= 1 100.0 100.0 0.0E+0 1.4012985E-43 0.0E+0 100.0 100.0 100.0
    j= 2 100.0 100.0 0.0E+0 1.4012985E-43 0.0E+0 100.0 100.0 100.0
    j= 3 100.0 100.0 0.0E+0 1.4012985E-43 0.0E+0 100.0 100.0 100.0
    j= 4 100.0 100.0 0.0E+0 1.4012985E-43 0.0E+0 100.0 100.0 100.0
    j= 5 100.0 100.0 0.0E+0 1.4012985E-43 0.0E+0 100.0 100.0 100.0
    Interestingly enough, recompile with m0 < 19 the results are fine (with or without -fast):
    m0= 18
    j= 1 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0
    j= 2 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0
    j= 3 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0
    j= 4 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0
    j= 5 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0
    The problem seems to be with the calculations of sum3i, sum4i, sum5i, all of which involve multiplying a real number (stored in rho) by the appropriate element of the integer mask (imask). Note that this result is peculiar to our Sun v60x; one of our other Suns:
    uname -a SunOS 5.8 Generic_108528-22 sun4u sparc SUNW,Sun-Fire
    f90 -V -fast subavsun.F -o subavf90: Warning: -xarch=native has been explicitly specified, or implicitly specified by a macro option, -xarch=native on this architecture implies -xarch=v8plusb which generates code that does not run on pre UltraSPARC III processors
    f90: Sun WorkShop 6 update 2 Fortran 95 6.2 2001/05/15
    fpp: Sun WorkShop 6 update 2 Fortran Utils 5.3 2001/05/15
    f90comp: Sun WorkShop 6 update 2 Fortran 95 6.2 2001/05/15
    f90: Cray CF90 Version 3.x.x.x (f41pXXgXXXa48) Tue Apr 19, 2005 11:32:53
    f90: COMPILE TIME 0.250000 SECONDS
    f90: MAXIMUM FIELD LENGTH 5018158 DECIMAL WORDS
    f90: 88 SOURCE LINES
    f90: 0 ERRORS, 0 WARNINGS, 0 OTHER MESSAGES, 0 ANSI
    iropt: Sun WorkShop 6 update 2 Compiler Common 6.2 Patch 111678-06 2001/12/10
    cg: Sun WorkShop 6 update 2 Compiler Common 6.2 Patch 111678-06 2001/12/10
    ld: Software Generation Utilities - Solaris Link Editors: 5.8-1.290
    gives good results. I'm not sure which element of -fast is causing the problem - with a bit of work I could probably narrow it down, but I thought people should be aware of the bug. Clearly the compiler is doing something strange.
    Thanks.
    Cheers,
    Mike
    Mike Casey
    Research Assistant
    Department of Oceanography
    Dalhousie University
    Halifax, Nova Scotia, Canada
    email: [email protected]
    work: phone: (902)494-2976
    FAX: (902)494-2885
    _____________________________________________________________

    I was able to reproduce your problem with the current studio 9 patch:
    f90: Sun Fortran 95 8.0 Patch 115985-02 2004/10/12
    f90comp: Sun Fortran 95 8.0 Patch 115985-02 2004/10/12
    f90comp: 86 SOURCE LINES
    f90comp: 0 ERRORS, 0 WARNINGS, 0 OTHER MESSAGES, 0 ANSI
    ir2hf: Sun Compiler Common 9.0 Patch 115982-04 2005/03/22
    ube_ipa: Sun Compiler Common 9.0 Patch 115982-04 2005/03/22
    ube: Sun Compiler Common 9.0 Patch 115982-04 2005/03/22
    ld: Software Generation Utilities - Solaris Link Editors: 5.9-1.380
    $ a.out
    m0= 19
    j= 1 100.0 100.0 0.0E+0 1.4012985E-43 0.0E+0 100.0 100.0 100.0
    j= 2 100.0 100.0 0.0E+0 1.4012985E-43 0.0E+0 100.0 100.0 100.0
    However, the test appears to run correctly with the studio 10 compiler.
    Peter Miller

  • Bug report: adding to contacts of received phone number or text

    Have highlighted selected phone number from caller log. Press hold on number to get side icons to show up on the right side of the screen. Selected add to contact icon. Gives me select screen of contacts. ??? Is this a bug or am I doing something wrong?

    Hello sevee, 
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    This is working as intended. You can either add the phone number to an existing contact or select the new option at the bottom of the screen to add to a new contact.
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  • Bug report: oracle.jbo.ViewCriteriaRow: string attribute value with '

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    [http://file.itpub.net/f/e38876ad4f6efb7e73980488e7d71f8d/4ae940e9/day_091029/20091029_2b04da1232144feba180OrB23SNvXtoT.gif/p/1.gif]
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    Patrick

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    The following file defines the ps7 wrapper when the ps7 instance is created in the BD
    $(XILINX_INSTALL_DIR)Vivado/2015.1/data/ip/xilinx/processing_system7_v5_5/ttcl/processing_system7.ttcl
    In this file the ENET GMII TX signals are *REMOVED*!!!  (They are commented out.)
    So I activated the signals and ethernet is working again.
    I have create a patch (see below) which shows the problem.
    So Xilinx, is any reasonable explanation out there for this? I guess a lot of mainboards requiere an EMIO Ethernet configuration.
    --- processing_system7.ttcl 2015-05-20 13:42:34.978734005 +0200
    +++ processing_system7.ttcl.org 2015-04-22 07:30:05.000000000 +0200
    @@ -1070,8 +1070,8 @@
    wire [11:0] M_AXI_GP1_RID_FULL;
    -wire ENET0_GMII_TX_EN_i;
    -wire ENET0_GMII_TX_ER_i;
    +//wire ENET0_GMII_TX_EN_i;
    +//wire ENET0_GMII_TX_ER_i;
    reg ENET0_GMII_COL_i;
    reg ENET0_GMII_CRS_i;
    @@ -1655,8 +1655,8 @@
    always @(posedge ENET0_GMII_TX_CLK)
    begin
    ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
    - ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i;
    - ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i;
    + ENET0_GMII_TX_EN <= 1'b0; //ENET0_GMII_TX_EN_i;
    + ENET0_GMII_TX_ER <= 1'b0;//ENET0_GMII_TX_ER_i;
    ENET0_GMII_COL_i <= ENET0_GMII_COL;
    ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
    end
    @@ -3134,9 +3134,9 @@
    .DMA3RSTN (DMA3_RSTN ),
    .EMIOCAN0PHYTX (CAN0_PHY_TX ),
    .EMIOCAN1PHYTX (CAN1_PHY_TX ),
    - .EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
    - .EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
    - .EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
    + .EMIOENET0GMIITXD (), // (ENET0_GMII_TXD_i ),
    + .EMIOENET0GMIITXEN (), // (ENET0_GMII_TX_EN_i),
    + .EMIOENET0GMIITXER (), // (ENET0_GMII_TX_ER_i),
    .EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
    .EMIOENET0MDIOO (ENET0_MDIO_O ),
    .EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
     

    Does not work for me.
    I re-run my 15.1 project in 15.2 and silll getting ENET1_TX pins tied to GND.
    Tried to re-generate block design, unset/set ENET1 - no effect.
    Tried to apply patch for 15.1 (added directory in D:\Xilinx\Vivado\2015.1\patches\AR64531_Vivado_2015_1_preliminary_rev1) then run in 15.1 - no effect
    I noticed that in processing_system7_v5_5_processing_system7 parameter C_EN_EMIO_ENET1 = 0, which blocks TX ports connection.
    Help needed.
     

  • Vivado 2015.2 warning about pipelining adder input

    Hello,
    I wrote RTL to perform a multiply-accumulate function (A*B+C), where either of the operators (mult or add) are optional. As such, it also performs A*B (without the addition to C) and (IN + C) functionally. The way this is performed in the RTL, is by selectively setting B to 1 if only an addition is required or C to 0 for mult only. So - 
    mode 1: A*B+C
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    mode 3: A*B+0
    mode 4: Acc only whereby the A input is accumulated with the PREG.
    I get the following warning in Vivado 2015.2 - 
    [DRC 23-20] Rule violation (DPIP-1) Input pipelining - DSP mac_/adder_/result_reg input B C is not pipelined. Pipelining DSP48 input will improve performance.
    My RTL is shown below. I've removed parts that are not relevant to this discussion (such as the code for the mode above, etc) - 
    assign mult_1_in = data_1_in_r; // data_1_in_r is 16 bit reg
    assign mult_2_in = opcode_1r < 2 ? 1 : data_2_in_r; // same for data_2_in_r
    always @(posedge clk) begin
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    end
    else begin // mult_bypass would be CREG of the DSP48E1
    mult_bypass <= opcode_1r < 2 ? data_2_in_r : 0;
    end
    end
    //mult instantiation here with sync reset and registered output (MREG)
    assign add_1_in = mult_out;
    assign add_2_in = opcode_2r == 0 ? mult_bypass :
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    // Adder instantiation here with registered output (PREG)
    So finally, my question is, is this just a warning or is it doing something funny because my code was not written correctly or is not able to be interpreted correctly by the tools?
    The device usage (with the netlist and all) is a bit confusing. It shows the C input being used. If that is the case, then it is registered (because the C input is always registered). So I'm not sure what the pipeline warning is about.
    EDIT: I was able to spot the following statements in the synthesis log - 
    DSP Report: Generating DSP mac_/adder_/result_reg, operation Mode is: (C+(A2*B)')'.
    DSP Report: register mac_/data_1_in_r_reg is absorbed into DSP mac_/adder_/result_reg.
    DSP Report: register mac_/adder_/result_reg is absorbed into DSP mac_/adder_/result_reg.
    DSP Report: register mac_/mult/result_reg is absorbed into DSP mac_/adder_/result_reg.
    DSP Report: operator mac_/adder_/result0 is absorbed into DSP mac_/adder_/result_reg.
    DSP Report: operator mac_/mult/result0 is absorbed into DSP mac_/adder_/result_reg.
    The adder's result register is PREG, the output. It should NOT be combined with MREG into one because the RTL does not specify this or anything remotely close anywhere. How/why is the output of the multiplier getting absorbed into the output of the adder? This is quite bizzare. 
    Thank you.

    I am pretty sure, it's just complaining about timing and there is no consequence about logic implementation. You can test the synthesis output gates and verify this. It is probably complaining about the mux you have at mult_2 and add_2_in. If you want the warnings to go away, register these variables.

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