What does "Locked" status really mean in FPGA Timekeeper

Question

The help says, "FPGA Timekeeper locked is TRUE if the FPGA Timekeeper has locked on to and is tracking the given time reference."
That's not very specific. 
- The Timekeeper is only "tracking the given time reference" when "Sync Time.vi" is called by the code, right?  Otherwise isn't it just predicting time base on the FPGA clock cycle, and apparently some filtering, gain and interpolation?  That wouldn't really be tracking the time reference.
- Is the Timekeeper checking the interval at which Sync Time.vi is called?
- Is it comparing the offset of the two time values input to Sync Time.vi  to its internal prediction?
- Is it making some judgement after a series of Sync Time.vi calls (how many?) that it has figured out the relative variations between the time reference and the FPGA clock?  How does it make that judgement?
- If a long time passes between Sync Time.vi calls does it decide it has lost its lock?
- Does calling Time Synce too frequently or too infrequently contribute to not achieving locked status, or to losing it?
Thanks for the help!  I love the idea of the FPGA Timekeeper but I don't know how to interpret the lock.  I can get the offset from the time reference, but what I'd really love to know is the size of the error when calling Time Synce.vi.

Answer 1

Hello Matt_Dennie,
The article below indicates that when using the FPGA Timekeeper with NI-9467 hardware, you will be able to correlate absolute time with system events at an accuracy of around 100 ns.
How Do I Use the FPGA Timekeeper to Synchronize Data with the NI 9467 GPS Module?:
http://ae.natinst.com/public.nsf/web/searchinternal/efdc35727d4f2cc086257a0700693003?OpenDocument
FPGA Timekeeper 1.1b0 GetStatus.vi:
http://forums.ni.com/t5/LabVIEW/FPGA-Timekeeper-1-1b0-GetStatus-vi-Locked-indicator-never-goes/td-p/...
The example VI for FPGA Timekeeper explains (briefly) the process used for synchronization (Synchronize to GPS – cRIO.lvproj). 
j_bou