How to simulate external hardware in LabView FPGA ?

Hello,
I have a NI 7952R connected to a 6583 IO module.
This IO module is connected to a digital sensor that continuously sends patterned data.
I am developping the code for the FPGA and I would like to know how to perform a cycle accurate simulation of the whole system.
There is an example for a cycle accurate simulation of the labView -> FPGA interface, but it doesn't include the behavior of an external hardware connected to the FPGA IO module.
Now I have a VHDL simulation model (not synthetisable) that describes my sensor. How to include that into the iSim cycle accurate simulation?
Do I have to alter the 6583 IO module CLIP files by including my sensor description into it?

Thank you for your answer, I think now we have a common understanding of your intent.
Your I/O simulation model is integrated via a clip or ip integration node:
"In addition to VHDL code for the FPGA VI, you must provide simulation models for any IP you include through the CLIP and IP Integration Nodes. You specify the models for CLIP simulation and the IP Integration Node simulation through their configuration wizards."
Taken from:
Introduction to Cycle-Accurate Simulation
http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_simulation_intro/

Similar Messages

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

How exactly does the memory in Labview Fpga work

I am using a PXI 7853 and I for the past few days I have been playing around with using Memory blocks in the FPGA .
Now I am relatively new to Labview FPGA programming and hence I would be grateful if someone could provide me with clarifications on teh following :
a) Since I am working on the development host computer when I initialize the Memory with the option of using a Memory initialization VI then how does it exactly happen in the backend .What I mean to ask is , when i change values of memory in the development computer and then compile the FPGA VI into the board ,is it that the Memory information is ported into the FPGA .If this is the case then in what form are the details initially saved in the development computer .
b) Is it possible for me to use the initialization VI method to change the valuesi n memory while the FPGA VI is running .If not ,then would it make a difference if I stop the VI and then change the values using initialization method .Would that actually reflect on the FPGA or should I have to re compile the FPGA VI every time I change the memory values in the development computer using the 'Initialization VI method ( that is available as an option when we right click on the memory block in the project explorer window )
I tried testing with simulation for FPGA VI and found that when i try to change the memory values by running the initialization VI . a pop up comes that says that it is not possible as the FPGA VI is still in use .
Any light on this or guidance with links would be highly appreciated
Cheers
sbkr
Solved!
Go to Solution.

sbkr wrote:
a) Since I am working on the development host computer when I initialize the Memory with the option of using a Memory initialization VI then how does it exactly happen in the backend .What I mean to ask is , when i change values of memory in the development computer and then compile the FPGA VI into the board ,is it that the Memory information is ported into the FPGA .If this is the case then in what form are the details initially saved in the development computer .
When you compile the FPGA VI, it will include the values used to initialize the memory.
Are you asking what happens if you run the FPGA VI on your development computer, and your FPGA VI writes to the memory block, will the new values be included when you compile the FPGA VI? No, those values will be lost. The values that are included in the bitfile are the values that you used to initialize the memory block, as defined in the memory properties dialog box. The initial values are saved in the LabVIEW project file along with the memory block definition.
sbkr wrote:
b) Is it possible for me to use the initialization VI method to change the valuesi n memory while the FPGA VI is running .If not ,then would it make a difference if I stop the VI and then change the values using initialization method .Would that actually reflect on the FPGA or should I have to re compile the FPGA VI every time I change the memory values in the development computer using the 'Initialization VI method ( that is available as an option when we right click on the memory block in the project explorer window )
You need to recompile the FPGA in order to use new initialization values, because those values are part of the FPGA bitfile.

How can I install (download) a Labview FPGA code onto Altera FPGA chip using Labview FPGA module?

Hi there
Guys i'm a very new labview user (PhD student), my project is about ( design and implementation of a high speed-yet sophisticated system using Labview environment then install this project's code (using Labview FPGA module) onto Altera-made FPGA chip).
so kindly, can any body help me in this?...is there any way to connect labview with Altera FPGA?...please anything would be said 'd be of great benifits
thanks a lot in advance.

as previously mentioned, labview fpga only supports national instruments targets utilizing xilinx fpgas. the hdl generated by labview fpga is encrypted and cannot be used to synthesize a design outside the labview fpga design flow.
however, if you must use labview for your project, it might be possible for you to design the system in labview and use one of the labview embedded modules ( http://www.ni.com/embedded )to generate c code which you can then port to systemc and compile for the altera fpga. i'm not saying it will be easy, but it should be possible.

How to connect external sensors to labview?

i want to ask How can i connect external sensors to NI labview for my final year project.? here are my lists of sensors:
a. Temperature sensor (LM35)
b. Humidity sensor (HH10D)
c. Light sensor (LDR)
d. Moisture sensor

simply_me wrote:
I've used the NI's bread board (with DAQ assistant initially) when I was in school. We used it for temp, light, and etc... measurements, the whole system is very straight forward. I would say having the option to simulate signals is a big plus in that. From what you described, I don't think the "slower" rate of data acquisition will disturb you at all. But more information is needed on your sensors and general functional spec.
@ NIquist & RTSLVU, please correct me if I'm misleading/wrong :-)
Is that the ELVIS stuff? Very neat but kind of pricey (unless the school is paying! )
Again, the low-cost USB DAQs from NI or MC are the way to go for the OPs project. I am assuming that he has enough electronics background to make simple signal conditioning circuits for his sensor chips.
Using LabVIEW: 7.1.1, 8.5.1 & 2013

How to simulate an lcd using labview

hi
i need to simulate a graphical lcd in pc using labview?(7.1).
i have posted this earlier and got replies.but i wish to know how to create the lcd screen?
i think i can make use of booleans.but i need the exact details for creating the graphical screen.
and on how to make each pixel glow(i.e., ON and OFF)
can anyone help me out in this issue..
regards
mahi

Hello Mahi,
I just jumped into this thread and remembered, that a few years ago I had a project to generate c-sources (actually header files to be included into c sources) to show custom made characters on an lcd display. As a side effect it creates what you need, a 3D- boolean array, where every 2D- portion holds a character.
With this program you can define the size of the character and alter it the way you need it. You can import a bmp- file with characters you need (e.g from a screen copy, must be a 1-bit bmp, black&white) and copy little frames from it to make work easier. If you click in the menu at "Fonts->Save Bool Spreadsheet" a text-file will be created which is in spreadsheet-style, where every cell (if you open it in Excel) consists of 0 and 1 according to the character. If you scroll down the front panel, you will find the 3D- Bool array which represents this data.
Just try it, the top-VI is "Fonts V2.vi", it should run properly. I put some screen-copy-bmp file and *.h- files into the zip to make the test easier for you.
I hope this helps,
Dave
Greets, Dave
Attachments:
Fonts.zip ‏998 KB

How to simulate external IP addresses on a single server Hyper-V test environment

I just bought a powerful laptop and installed a spare copy of Server 2012 R2 Datacentre on it.
I am in the process of setting up a test LAN with DC, Exchange, TMG firewall web and backup servers.
V host without the use of external physical routing?
I would like to connect a client to the LAN services such as Exchange and VPN in the same way a client device connects to a network over the internet. In other words, I need to test the external IP addresses of my test LAN.
I am considering a setup consisting of two separate LANs with different IP address ranges:
LAN 1: internal network (with all the services mentioned above)
LAN 2: with only one client VM; this would be the external network (simulated internet)
Is this the best way of doing it? Has anyone already done something similar?
Many thanks!

I have something similar.
I don't believe your solution would work alone, as you'd need a VM to act as a router between the two. You could do it like that (but adding a virtual router) or you could just let WAN be your local network (the one your laptop is on)
Some steps (not very detailed, I can provide my documentation I wrote for Hyper-V running on server 2012 R2 (should work exactly the same for you though)
The first vSwitch created should be External type (it should already be created if you installed Hyper-V)
Create a second switch, call it whatever (Internal or LAN doesn't matter), set it's type to Private.
Create a small 512MB Generation 1 VM with a small (1GB should be fine, and it can be dynamic expanding)
Add two LEGACY (key point) network adapters to it, attach the first to the external and the second to the private.
Install pfSense onto it. You'll basically have a router. the first interface is the WAN (if you set the first adapter as external when you added them to the VM) or "the internet" you could say. While the private switch is the second interface or your local
(private) LAN. Now any VM you want to be on this virtual LAN just set it's network adapter to be connected to the Private vSwitch.
I have instructions if you want to do this (specifically for Hyper-V (I wrote them in case I ever had to reinstall it because there are a few gotchas with it being virtualized)

How to simulate pwm wave using labview

has anyone have a built vi for pulse width modulation(PWM),or give me pointer in building its simulation

Hi,
If you just want to generate a PWM signal you can use a square waveform VI as shown in attachment. You can insert it directly in your code or create a subVI as you need.
Message Edité par BenjaminR le 03-06-2008 04:23 AM
Benjamin R.
R&D Software Development Manager
http://www.fluigent.com/
Attachments:
PWM generation.jpg ‏28 KB

Why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?

Dear Friends,
Since I have started using LABVIEW FPGA, I got too many questions in my mind looking for answers!
1-      Does anybody can tell me “why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?”
I mean there are many great tools in this field (e.g. Xilinx ISE, ….); what makes LABVIEW FPGA the perfect tools that can save my time and my money?
I’m looking for a comparison can show the following points:
·         The Code size and speed optimization.
·         Developing time.
·         Compiling time.
·         Verifying time.
·         Ability to developing in future.
·         …etc.. 2-
I’ve Spartan-3E kit, I’m so glad that LABVIEW support this kit; I do enjoyed programming the kit using LABVIEW FPGA, but there are too many obstacles!
The examples come with Spartan-3E driver don't cover all peripherals on board (e.g. LAN port is not covered)! There is a declaration at NI website which is "LabVIEW FPGA drivers and examples for all on-board resources" Located at: http://digital.ni.com/express.nsf/bycode/spartan3eI don’t think that is true!
Anyway, I will try to develop examples for the unsupported peripherals, but if the Pins of these peripherals are not defined in the UCF file, the effort is worthless! The only solution in this case is to develop VHDL code in ISE and use it in Labview FPGA using HDL node!?
3-      I wonder if NI has any plan to add support for Processor setup in Labview FPGA (Like we do in EDK)?
4-      I wonder if NI has any plan to develop a driver for Virtex-5 OpenSPARC Evaluation Platform ?http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,599&Prod=XUPV5
Thnaks & regards,Walid
Solved!
Go to Solution.

Thanks for your questions and I hope I can answer them appropriately
1. LabVIEW FPGA utilizes the intuitive graphical dataflow language of LabVIEW to target FPGA technology. LabVIEW is particularly nice for FPGA programming because of its ability to represent parallelism inherent to FPGAs. It also serves as a software-like programming experience with loops and structures which has become a focus of industry lately with C-to-gates and other abstraction efforts. Here are some general comparison along the vectors you mentioned
Code Size and speed optimization - LabVIEW FPGA is a programming language. As such, one can program badly and create designs that are too big to fit on a chip and too slow to meet timing. However, there are two main programming paradigms which you can use. The normal LabVIEW dataflow programming (meaning outside a single-cycle loop) adds registers in order to enforce dataflow and synchronization in parity with the LabVIEW model of computation. As with any abstraction, this use of registers is logic necessary to enforce LabVIEW dataflow and might not be what an expert HDL programmer would create. You trade off the simplicity of LabVIEW dataflow in this case. On the other hand, when you program inside a Single-Cycle timed loop you can achieve size and speed efficiencies comparable to many VHDL implementations. We have had many users that understand that way LabVIEW is transformed to hardware and program in such a way to create very efficient and complex systems.
Development Time - Compared to VHDL many of our users get near infinite improvements in development time due to the fact that they do not know (nor do they have to know) VHDL or Verilog. Someone who knows LabVIEW can now reach the speeds and parallelism afforded by FPGAs without learning a new language. For harware engineers (that might actually have an alternative to LabVIEW) there are still extreme time saving aspects of LabVIEW including ready-made I/O interfaces, Simple FIFO DMA transfers, stichable IP blocks, and visualizable parallism. I talk to many hardware engineers that are able to drastically improve development time with LabVIEW, especially since they are more knowledgable about the target hardware.
Compilation Time - Comparable to slightly longer to due to the extra step of generating intermediate files from the LabVIEW diagram, and the increased level of hierarchy in the design to handle abstraction.
Verification Time - One of our key development initiatives moving forward is increased debugging capabilities. Today we have the abilities to functionally simulate anything included in LabVIEW FPGA, and we recently added simluation capabilities for Imported IP through the IP Integration node on NI Labs and the ability to excite your design with simulated I/O. This functional simualation is very fast and is great for verification and quick-turn design iteration. However, we still want to provide more debugging from the timing prespective with better cycle-accurate simulation. Although significantly slower than functional simulation. Cycle-accuracy give us the next level of verification before compilation. The single cycle loop running in emulation mode is cycle accurate simluation, but we want more system level simulation moving forwrad. Finally, we have worked to import things like Xilinx chipscope (soon to be on NI Labs) for on-chip debugging, which is the final step in the verification process. In terms of verification time there are aspects (like functional simulation) that are faster than traditional methods and others that are comparable, and still other that we are continuing to refine.
Ability to develop in the future - I am not sure what you mean here but we are certainly continuing to activiely develop on the RIO platform which includes FPGA as the key diffentiating technolgoy.  If you take a look at the NI Week keynote videos (ni.com/niweek) there is no doubt from both Day 1 and Day 2 that FPGA will be an important well maintained platform for many years to come.
2. Apologies for the statement in the document. The sentence should read that there are example for most board resources.
3. We do have plans to support a processor on the FPGA through LabVIEW FPGA. In fact, you will see technology on NI Labs soon that addresses this with MicroBlaze.
4. We do not currently have plans to support any other evaluation platforms. This support was created for our counterparts in the academic space to have a platform to learn the basics of digital design on a board that many schools already have in house. We are currently foccussing on rounding out more of our off-the-shelf platform with new PCI Express R Series boards, FlexRIO with new adapter modules, cRIO with new Virtex 5 backplanes, and more.
I hope this has anwered some of the questions you have.
Regards
Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
Check out the FPGA IPNet for browsing, downloading, and learning about LabVIEW FPGA IP Cores

LabView fpga VHDL code and compiler

Hello,
I'm in the project where we would like to use NI hardware (more likely cRIO system). With NI hardware we will read/wright several AI/AO and DIO and perform some math and controls on the result of readings. We are planning to design FPGA code for project, but we are thinking about implement all data processing and control logic in VHDL and link it with AI, AO and DIO with help CLIP or IP Integration Node as explained in this : "white-paper": http://www.ni.com/white-paper/7444/en/
Mentioned above paper explain how to implement VHDL code in LabVIEW FPGA VI using CLIP or IP Integration Node, but the topic that is not highlight explicitly is how these construction CLIP and IP Integration Node will be handled by Compiler. The main reason for such approach (VHDL linked with part that read/write into hardware AI AO and DIO) we expect that our VHDL code will be handled by LabVIEW compiler without modification and passed to Xilinx Compiler synthesis as is (path for Compile process I've taken from here: http://www.ni.com/white-paper/9381/en/ ), so we will be able at some level bypass the intermediate process of compilation and get almost the same result as if we design pure VHDL code and use Xilinx ISE for Synthesis Mapping and Bit File generation.
Will this approach work? I was not able to find any documents that explain the Compiler behavior and confirm that VHDL code handled untouched or will modified, does such document exist?
Note. I've requested official assistance from NI support on topic above, but I would like to post this question on forum hoping get more feedback.

Hello RangerOne,
There won't be any modications to the internal logic of the VHDL that you implement in the IP integration node. Though I've seen developers unfamiliar with LabVIEW FPGA get tripped up on the synchronization registers that LabVIEW FPGA inserts into the code around the integration node. Learning where and why these syncrhonization registers are inserted has in my experience always resolved this issue. These two help documents do a good job of explaining the 'where and why' of synch registers when the enable chain is present, or when working with IO inside of a SCTL.
With regards to the stability of LabVIEW FPGA, I would second Daniel's sentiments. What about the known issues list conveys instability and risk? As a point of comparison, here are the known issues for ISE 14.x.
If you are looking to minimize risk, I would recommend developing the critical logic in the development enviroment in which you are comfortable setting up a comprehensive test bench since testing the code is the only way to truly verify its functionality. For me this would be LabVIEW FPGA as it has excellent trouble shooting tools and I've been developing in it for quite some time. Perhaps you're more familiar with ISE than LabVIEW FPGA and that is the source of your trepidation? If that is the case then you may find the High Performance FPGA Developers Guide a good read. You may also find a few of the case studies on our website reassuring since they demonstrate other teams successfully implementing a solution using LabVIEW FPGA. Here's one that used LabVIEW FPGA in conjnction with VHDL IP similiar to what you are doing.
National Instruments
FlexRIO Product Support Engineer

How to use LabVIEW FPGA on Custom FPGA board other than NI products .....Also how to develop RTx DLL for a customised motion controller hardware

I'm using RTx, LabVIEW RT and LabVIEW FPGA.
The GUI is windows based. The motion control and FPGA are RTx based.
Is there any way to develop device drivers for the custom hardware in RTx. For example motion controller hardware, FPGA hardware, PCI hardware.
Is there a possibility to use custom FPGA boards to use with LabVIEW FPGA.
Please send me some links
Thanks
Bhoopathy
Take life as it comes! you may never know what's gonna happen Tommorrow

CODE WARRIOR Hello. I believe this question was answered in a previous post. Please let us know if you have any new questioins or if you need some clarification.
You are able to develop device drivers for your custom hardware using the NI Measurement Hardware Driver Development Kit.
However, it is not possible to use custom FPGA boards with LabVIEW FPGA. The FPGA boards have to be one of our R Series boards. Here are some links that should shed some light on the Measurement Hardware DDK.
Measurement Hardware Driver Development Kit Frequently Asked Questions
NI Measurement Hardware DDK (Driver Development Kit)
Please post if you have further questios.
Efosa O.
NIAE

Labview program to find the external hardwares connected with the PC

Hai All,
Do any one know how to find the external hardware details connected with our PC (like USB memory stick), using labview program.

That's assuming the user is running Windows.
If you are under Windows you can access this information from the Registry. For example, for USB you can look at the key
HKEY_LOCAL_MACHINE\SYSTEM\ControlSet001\Enum\USB.
Message Edited by smercurio_fc on 04-30-2008 10:39 AM

Dear frnz, i am doing my prjct in Lview. ie online PQ monitoring. i need to simulate the system with disturbances generated in Lview. so can any bdy plz tel me how to genrte PQ problems in labview. thanks in advance..

dear frnz, i am doing my prjct in Lview. ie online PQ monitoring. i need to simulate the system with disturbances generated in Lview. so can any bdy plz tel me how to genrte PQ problems in labview. thanks in advance..

I work in the power conversion industry and do these types of measurements all the time…
Do you want to just measure power quality or create and measure power quality problems?
What hardware are you using?
Power quality analyzer?
Programmable AC power source?
Fast Transient Generator?
Here is an example of what I do.
To create PQ problems I use a California Instruments AC source set to nominal power for the unit under test. Using Labview I program several transients consisting of fixed and random duration dropouts and surges. I also use a Schaffer Fast Transient Burst Generator to apply high frequency noise bursts directly onto power lines.
For measuring power quality I use a Voltech PM3000A power analyzer and Labview to measure everything from voltage, current, and frequency, to harmonics and %THD
Message Edited by RTSLVU on 07-23-2008 10:31 AM

How to simulate a DAQ device and use it for testing applications without hardware???

how do i simulate a DAQ device
in MAX and use it for testing applications without hardware???
If my application requires inputs
from external hardware to proceed how can I simulate a DAQ device in LabVEIW?
i need to simulate several Digital inputs and Outputs to test the software. currently i dont have the hardware and DAQ device here.
please reply with your valuable suggestions.
many thanks in advance
RENN
Kudos always welcome for helpful posts
Solved!
Go to Solution.

Hi,
There is no option to simulate traditional device.You need hardware for that so i would suggest to simulate a PXI device which has similar configuration to PCI-6014 and to do a small modification to your application..

How to generate a chirp(linear FM) signal using dds theory in LabVIEW FPGA.

how to generate a chirp(linear FM) signal using dds theory in LabVIEW FPGA.
attachment:a sine signal using dds theory. Hope to get some help. Thanks!
Attachments:
FPGA DDS SineGen IP.vi ‏42 KB

you need to increment the "accumulator increment" during the duration of the chirp. the "accumulator increment" controls the frequency of the DDS cycle. by increasing it's value, you are increasing the frequency. the math for increment values follows the same math as determining the frequency to increment value.
Stu McFarlane
Viewpoint Systems, Inc.

How to simulate external hardware in LabView FPGA ?

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