1473R DMA timeout at high speed?

I'm using a 1473R with a Basler line camera spl2048-140km. I managed to modify the example to run the camera on both 8 tap 8 bit mode and 4 tap 12bit mode. Both run well at low speed. However, there are two issues when I try to run it at high speed.
If I set the frame trigger at relatively high speed before I start the acquiring (like 30kHz), a DMA timeout error will jump out as soon as I start it (error -8999). If I set it at low speed (like 100Hz), it will run fine as I increase it to 30kHz after it starts.
Another issue is, when I try to push the speed of the camera to its limit, which is 70kHz for single channel mode and 140kHz for dual channel mode, I will always have the error -8999. It happens when the speed reaches 100kHz in 8 tap 8 bit mode, and 50kHz at 4 tap 12 bit mode. I wonder where the bottle neck is and if there will be a way to solve it.
Thanks!

I'm not that familiar with the FPGA code for the 1473R, but I am fairly sure that the DRAM example has been tested with fairy fast cameras. That said, it seems from looking at it that it does not have a good feedback mechanism if PCIe bandwidth is not available. It's only feedback seems to be if the host DMA buffer fills up (e.g. host code doesn't read it fast enough). Since PCIe/memory bandwidth is extremely host-dependent, it is quite possible this example is not well tested with the combination of very fast cameras and some systems that have more jittery PCIe bandwidth. I'm not sure of the specifics of the DMA FIFO behavior, but my assumption is that the number of elements remaining really only concerns itself with host space available. For most situations, the minimal amount of FIFO built into the DMA engine likely makes this work fine.
First, I'd try instrumenting the code to figure out which specific part in the FPGA code is timing out. The example doesnt seem to track all the error cases well.
Assuming it is the host DMA that times out AND it always reports that there is free space available, my suggestion would be to modify the code to let the DMA step retry with the same data the next clock cycle on a Timeout and let the data back-up in DRAM as needed.
Eric

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    997-EoSens 3CL-MC1362-Manual.pdf ‏1209 KB

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    HSC in motion activate the start of imaq in second loop.vi ‏72 KB
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