5122 sampling, decimation & sunchronization

Question

Syatem configuration:
1. 8 slot PXI system
2.Five 5122 14-bit digitizer cards
3. one 6602 counter/timer card
Q1. is it possible to synchronize the system to a 10MHz standard
frequency (external to the system). is it possible to synchronize the
sampling frequency of all the 5122 and clock output of 6602 can be
synchronized to the externally supplied 10MHz referecne clock.
Q2. What is decimation in 5122? the datasheet says minimum sampling
frequency as 30MSPS then how the digitizer samples at frequencies less
than this
Q3. 50ohm cable driving capability of 5122 sampling clock output

Answer 1

Hello ,
I would like to answer your question that you posed. Please let me know if you have further questions.
A1: Yes it is possible to synchronize the 5122 cards with an external clock (10MHZ signal). You could either use this external signal as the source of your sample clock or use it as a reference signal. The backplane of the chassis could also serve as a reference signal for your acquisition.
A2: Decimnation is well explained in the NI High Speed Digitizers Help file. I copied and pasted the Sample clock section of the help file. In the case of the 5122, decimnation is allowed with external clocks.
Sample Clock
The sample clock is sent to the ADC of each channel and to the acquisition engine to control the sampling rate of a digitizer. The sample clock sources are as follows.
A3: I would appreciate further details on what is needed here. Are you looking for some specifications about transmission capabilities?
Internal Sample Clock
High-speed digitizers and oscilloscopes have an onboard (internal) clock that controls the sampling rate as well as other timing functionality of the device. In most cases, the onboard oscillator is a Voltage Controlled Crystal Oscillator (VCXO). Typically, an onboard DAC (digital to analog converter) is used to calibrate the VCXO to exactly the desired clock rate. This DAC can also be used to adjust the frequency of the VCXO to phase lock it to a reference clock The maximum sampling rate of a device is usually determined by the speed of the onboard clock. However, other sampling rates can be achieved by two methods; decimation of the data or dividing down the onboard clock.
Decimation Method
In the decimation method, the ADC samples at the rate of the onboard clock and then sends its digital data to a decimator that essentially discards samples at a specific interval to achieve slower effective sampling rates. The valid sampling rates are always an integer divisor of the onboard clock. For example, if the onboard clock is 100 MHz but you want to sample at 25 MS/s, you must use decimation. The decimation method would discard all data except for every fourth datapoint to achieve exactly 1/4 of the maximum sample rate (or onboard clock rate).
Divide Down Clock Method
In the divide down clock method, the onboard clock is sent through a series of clock dividers, and then that clock is sent to the ADC. Typically, the decimation method is preferred over the divide down clock method.
External Sample Clock
Some digitizers and oscilloscopes can accept an external sample clock. This external sample clock is used to replace the onboard clock (the VCXO) for synchronization or to achieve a sampling rate that cannot be specified by using the onboard clock. Some devices can also decimate the external sample clock to achieve a sampling rate that is an integer divisor of the external sample clock. For example, if the external sample clock is 70 MHz, you could decimate the clock by a factor of 2 and achieve a 35 MS/s sampling rate.
Ayman K