6602 register level settings to latch encoder on RTSI trigger

Greetings,
I am currently using the
6602, comedi driver, and real time linux to read 6 quadrature
encoders. I would like to add some functionality to the comedi driver
that would latch the encoder values from a RTSI trigger. I have the
register programming manual for the 6602; However, I am not quite sure
how I should set up the registers for this task. If someone could help me figure out what bits need to be set in the 6602 registers, it would be
greatly appreciated.
Thanks,
Greg

Hi Greg -
I won't be able to help you with the Comedi driver, but I did find this KnowledgeBase article about it: KB 31GGUUBG
Among the things mentioned in the article are these:
- The driver doesn't support counters
- NI-DAQmx Base for Linux is a recommended, fully NI-supported alternative driver
If you need to continue using Comedi anyway, you might want to post your question in the MHDDK forum. If anybody can help you, they're the most likely.
David Staab, CLA
Staff Systems Engineer
National Instruments

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PXI-6602 Register Level Initialization

I am trying to program a PXI-6602 using Registry Level Programming.
It is hooked up to a BNC-2121 so I can check activity.
I would like to know how to
   1. Configure the DIO_! through DIO7 as Outputs. The manual says to write registers BAR1 Offset 0x77C and 0x780 with 0x02020202.
       This seems to work.
    2.

I am trying to program a PXI-6602 using Registry Level Programming.
It is hooked up to a BNC-2121 so I can check activity.
I would like to know how to
   1. Configure the DIO_! through DIO7 as Outputs. The manual says to write registers BAR1 Offset 0x77C and 0x780 with 0x02020202.
       This seems to work.
    OOps - I got shipped out
   2. When I try to Write to the published IO Registers the unit doesn't write to the outputs.
        This board works fine using MAX, so I know it is pilot error.

Setting 6602 registers to latch encoder values on RTSI trigger

Greetings,
I am currently using the 6602, comedi driver, and real time linux to read 6 quadrature encoders. I would like to add some functionality to the comedi driver that would latch the encoder values from a RTSI trigger. I have the register programming manual for the 6602; However, I am not quite sure how I should set up the registers for this task. Any help would be greatly appreciated.
Thanks,
Greg

Thanks Tom and David for your help.
I have looked over the examples that Tom listed and I think I understand the necessary register settings. Just in case I missed something I have includded an example configuration and read function for your review. The configuration is a combination of gpct_ex7.cpp and gpct_ex8.cpp. Also, am I correct in assuming that if using a RTSI signal to latch the encoder values that the encoder index can not be used to reset the counter? It seems they would both need access to the gate.   Thanks again for your help,
Greg
// configuring 6602...
void test(iBus *bus)
   tAddressSpace cardSpace;
   tTIO *board;
   cardSpace = bus->createAddressSpace(kPCI_BAR1);
   board = new tTIO(cardSpace);
   //Reset
   board->G01_Joint_Reset_Register.writeG0_Reset(1);
   //Disarm
   board->G0_Command_Register.writeG0_Disarm(1);
   //load initial value of 0
   board->G0_Load_A_Registers.writeG0_Load_A(0x00000000);
   board->G0_Command_Register.writeG0_Load(1);
   //set the counting mode to quadrature encoding X4
   board->G0_Counting_Mode_Register.setG0_Encoder_Counting_Mode(3);
   //set source to the internal timebase (20 MHz)
   board->G0_Input_Select_Register.writeG0_Source_Select(0);
   //set gate to latch encoder value on rising edge of RTSI 0
   board->G0_Input_Select_Register.writeG0_Gate_Select(11);
   board->G0_Mode_Register.writeG0_Gate_Polarity(0);
   board->G0_Mode_Register.writeG0_Gating_Mode(2);
   board->G0_Mode_Register.writeG0_Trigger_Mode_For_Edge_Gate(3);
   //set counting direction to Gate IO connector
   board->G0_Command_Register.writeG0_Up_Down(2);
   //use the DMA registers as a two element FIFO
   //The TIO will alternate save locations between the HW save and SW
   //save registers.
   board->G0_DMA_Config_Register.writeG0_DMA_Enable(1);
   board->G0_DMA_Config_Register.writeG0_DMA_Int_Enable(1);
   //arm counter
   board->G0_Command_Register.writeG0_Arm(1);
// reading the counter value would go something like this...
void generic_read(tTIO *board)
   int HWsaveOrSWsave;
   //the DMA Read register tells us where the most recent sample was saved:
   // 1 for SW save register, 0 for the HW save register
   HWsaveOrSWsave = board->G0_DMA_Status_Register.readG0_DMA_Read_Register();
   if(HWsaveOrSWsave == 1)
       printf("SW Save Register is 0x%08lx\n",
           board->G0_Save_Registers.readRegister());
   else
       printf("HW Save Register is 0x%08lx\n",
           board->G0_HW_Save_Registers.readRegister());

Ni 6602 Card, Configuration in Register Level Programming

Hello,
I want to do register level programming with the NI 6602 card .
I want to use an x4 encoder reader and I want to use the continuous
frequency generation.
so i got the following tool to map the kernel space to the user space, so
a simple shell script will do the job.
http://www.linux.it/~rubini/software/phob/phob.html
and than just using the provided function phob_io
to programm the registers in a shell script:
#!/bin/bash
# shell script for init 6602 card with prf and encoder counter
# set prf
../phob_io ''0:048=0000'' # Input Select Register
../phob_io ''0:00C=1109'' # Command Register
../phob_io ''0:038=00ffffff'' # Load A Register
../phob_io ''0:03C=00ffffff'' # Load B Register
../phob_io ''0:
034=9218'' # Mode Register
But don"t get any output as i expect, what is wrong?
Do i have to set some othe registers, or write somthing to the PCI-Config?
Does anyone has some sample configuration?
Thanks
Mario Behn
Mario Behn
Microwave Remote Sensing Laboratory Room 104
University of Massachusetts
Knowles Engineering Building
Amherst, MA 01003-4410
phone (413) 545-4675
fax (413) 545-4652
email [email protected]

A typical project for one of the 660x RLP examples needs to include the following source code files:
../OSinterface/osiBus.cpp - generic register I/O interface used by the example code
../OSinterface/Linux/osiUserCode.cpp - OS specific adapter used by osiBus to access registers on the hardware in the specific OS
../ChipObjects/tTIO.cpp - abstraction of the chips and registers on the hardware into C++ classes and properties
and one of the examples files, e.g.
../Examples/gpct_ex1.cpp - implementation of a specific operation, including all initialization of the hardware
(The same is true for the examples for other boards although the names of the ChipObject and examples will be different.)
Each of these files needs to be compiled to give y
ou object files, and then all of the object files need to be linked together to build an application (executable binary). The errors you list seem to indicate that you are not using all of these files.
There is more information on the RLP example architecture in the attached PDF document.
Christian Loew, CLA
Principal Systems Engineer, National Instruments
Please tip your answer providers with kudos.
Any attached Code is provided As Is. It has not been tested or validated as a product, for use in a deployed application or system,
or for use in hazardous environments. You assume all risks for use of the Code and use of the Code is subject
to the Sample Code License Terms which can be found at: http://ni.com/samplecodelicense
Attachments:
Register_Level_Programming_Architecture.pdf ‏165 KB

Ni 6602 Card, Configuration DIO and Counter in Register Level Programming

Hello,
I want to do register level programming with the NI 6602 card .
Which register determine a channel act as DIO or Counter.

Hi:
please refer to this link,why not using DAQmx driver?
NISH AE
Haifeng Xu

JRE System-level settings does not work - JRE1.6.30

Good day,
I need to set deployment.security.mixcode parameter to "DISABLE" within of deployment.properties configuration file.
Also I wish to place the deployment.properties configuration file is not user-specific path. The default location is
<User Application Data Folder>\Sun\Java\Deployment\deployment.properties.
TO change the default location I read about possibility to use the deployment.config for specifying the System-Level
deployment.properties in the infrastructure.
Unfortunatelly seems does not work. Someone have got experience about system level settings of deployment.properties?
This is the configuration I have used.
deployment.config:
deployment.system.config.mandatory=FALSE
deployment.system.config=file/:C:\Program Files\Java\jre6\lib\deployment.properties
deployment.properties:
#deployment.properties
#Fri Feb 17 15:54:57 CET 2012
deployment.version=6.0
deployment.capture.mime.types=true
deployment.browser.path=C\:\\Program Files\\Internet Explorer\\iexplore.exe
#Java Deployment jre's
#Fri Feb 17 15:54:57 CET 2012
deployment.javaws.jre.0.product=1.6.0_31
deployment.javaws.jre.0.registered=true
deployment.javaws.jre.0.osname=Windows
deployment.javaws.jre.0.platform=1.6
deployment.javaws.jre.0.path=C\:\\Program Files\\Java\\jre6\\bin\\javaw.exe
deployment.javaws.jre.0.location=http\://java.sun.com/products/autodl/j2se
deployment.javaws.jre.0.enabled=true
deployment.javaws.jre.0.osarch=x86
deployment.security.mixcode=DISABLE <<====
Thank you in advance
Adriano C.
Edited by: user12025469 on Feb 20, 2012 6:23 AM
Edited by: user12025469 on Feb 20, 2012 7:48 AM

user12025469 wrote:
This is the configuration I have used.
deployment.config:
deployment.system.config.mandatory=FALSE
deployment.system.config=file/:C:\Program Files\Java\jre6\lib\deployment.propertiesHm, try using a file URL like this:
file\:C:/Program Files/Java/jre6/lib/deployment.propertiesI believe that the file is interpreted as a properties file, which means the colon and slashes need to be escaped. This would be it if you want to use a proper Windows path:
file\:C:\\Program Files\\Java\\jre6\\lib\\deployment.properties

660x DIO Register Level Programming

I am working on a comedi/linux driver for the 6602, and can't figure out how to access the other 24 DIO lines (the ones shared with counter/timer).
Firstly, I want to use the DIO lines for output, so I must configure them as such. The RLPM doesn't say anything more than a hint about how to configure these lines .
It seems the answer lies in using 2 bits to set to IO_Config Register(s). The RLPM says that these registers contain 2 bits for configuration direction, but only lists functionality for 00 and 01; not 10 or 11. Is it possible that setting 11 or 10 sets these PFI lines for DIO?

Hello!
We don't do support on register-level programming but the problem you are experiencing might be due to tri-state on the ports?
Please check this manual that covers register programming of the device you are using:
http://digital.ni.com/manuals.nsf/websearch/47300C3471742AD0862570AE005E0AD1
Regards,
Jimmie Adolph
Systems Engineer Manager, National Instruments Northern Region
Bring Me The Horizon - Sempiternal

Pad synchronization register level programming

Dear all,
the user manual (6602) talks about pad synchronization. I need six counters to start generating PWM - Signals at the exact same point of time. An external trigger should be used. As pointed out in the user manual, the external trigger is connected to PFI 38, the counters have PFI 38 selected as their gate. I've managed to trigger the PWM Signals, but they are NOT synchronized. In fact I could observe quite a huge time delay between the PWM - Signals. Can you tell me, which bit i need to change on register-level ? Pad Synchronization is not mentioned in the RLPM.
Thanks,
Nico

I'm not sure if pad synchronization will address Nico's symptoms. As the manual points out on page 13 (Ch 2, pg 2) [1], pad synchronization normalizes propagation delays in the board from the I/O pins to the counters' inputs on the TIO ASIC. However, propagation delays are never more than the period of the fastest timebase on the board (otherwise pad synchronization couldn't be called a feature ;-). Since Nico mentioned seeing "quite a huge time delay between the PWM - Signals", I believe he's facing a different kind of synchronization problem.
My question is: do any of you folks observe asynchronicity due to propagation delay? In other words, is the maximum time between one PWM starting and a second PWM starting equal to the period of the clock on the counter's source? You may just need to use the same signal (provided either externally or internally) to arm-start the counters instead [2].
[1] 660x User Manual
http://digital.ni.com/manuals.nsf/websearch/3751AB99F196F6738625768C001307AF
[2] What are the 3-bit field choices for Hw_Arm_Sel in PCI-6601
http://forums.ni.com/ni/board/message?board.id=90&view=by_date_ascending&message.id=1638#M1638
Joe Friedchicken
NI VirtualBench Application Software
Get with your fellow hardware users :: [ NI's VirtualBench User Group ]
Get with your fellow OS users :: [ NI's Linux User Group ] [ NI's OS X User Group ]
Get with your fellow developers :: [ NI's DAQmx Base User Group ] [ NI's DDK User Group ]
Senior Software Engineer :: Multifunction Instruments Applications Group
Software Engineer :: Measurements RLP Group (until Mar 2014)
Applications Engineer :: High Speed Product Group (until Sep 2008)

How to do register-level programming for NI6025E when I want to acquire single scan incuding multiple input channels?

How to do register-level programming for NI6025E when I want to acquire single scan incuding multiple input channels?

Thanks, Alan, I think I indeed need to combine aiex1.cpp and aiex2.cpp. I made a change to Configure_Board of aiex1.cpp as follows:
//Call this function to configure board options.
void Configure_Board(tSTC *theSTC,tESeries *board)
//Clear configuration memory
theSTC->Write_Strobe_0.writeRegister(0x0001);
//Clear ADC FIFO
theSTC->Write_Strobe_1.writeRegister(0x0001);
//Writing to Config_Memory_High_Register for channel 1 settings
board->ConfigFifoHigh.setChannel(0);
board->ConfigFifoHigh.setBank(0);
board->ConfigFifoHigh.setChannelType(board->ConfigFifoHigh.kChannelTypeRSE);
board->ConfigFifoHigh.flush();
//Writing to Config_Memory_Low_Register for following channel 1 settings
board->ConfigFifoLow.setLastChannel(0);
board->ConfigFifoLow.setGeneralTrigger(0);
board->ConfigFifoLow.setGain(board->ConfigFifoLow.kGain001_0);
board->ConfigFifoLow.setPolarity(board->ConfigFifoLow.kPolarityBipolar);
board->ConfigFifoLow.setDither(0);
board->ConfigFifoLow.flush();
//Writing to Config_Memory_High_Register for following channel 0 settings
board->ConfigFifoHigh.setChannel(1);
board->ConfigFifoHigh.setBank(0);
board->ConfigFifoHigh.setChannelType(board->ConfigFifoHigh.kChannelTypeRSE);//RSE mode
board->ConfigFifoHigh.flush();
//Writing to Config_Memory_Low_Register for following channel 0 settings
board->ConfigFifoLow.setLastChannel(1);
board->ConfigFifoLow.setGeneralTrigger(0);
board->ConfigFifoLow.setGain(board->ConfigFifoLow.kGain001_0);
board->ConfigFifoLow.setPolarity(board->ConfigFifoLow.kPolarityBipolar);//BIPOLAR
board->ConfigFifoLow.setDither(0);
board->ConfigFifoLow.flush();
return;
and a change to test(iBus *bus):
do
  uStatus = theSTC->AI_Status_1.readRegister();
  if (!((uStatus & 0x1000) == 0x1000))
  uValue[i] = board->AIFifoData.readRegister();
   i++;
} while(i<1);
printf("Value %d is %6.2f\n",0,FindADDouble(uValue[0]));
printf("Value %d is %6.2f\n",1,FindADDouble(uValue[1]));
but it doesn't work, why?
How shoud I do?

Timebase signal to pfi 0 to 7 pin (register level)

Hi,
I wonder if someone can help me. I am using a PCI-6602 card as a counter/timer. I would like access to the internal timebase signal via a PFI pin so that I can use that clock to sync another device.
I have just got off the phone with NI who were exceptionally helpful and said that it is possible to "route" a signal to the PFI pin.
However, I am using register level programming (as I am in linux) and cannot find any information in the register level programming manual.
Does anyone know how to do this? Or the register that needs to be set?
Many thanks,
Stuart

Hi Stuart-
Which Linux distribution are you using? If it's one of the supported distros, I would recommend that you use NI-DAQmx 8.0 for Linux. The functionality to route PFI signals is available in NI-DAQmx via the DAQmxExportSignal() and DAQmxConnectTerms()/DAQmxDisconnectTerms() functions.
Hopefully this helps-
EDIT: If you still need help with register-level programming, please repost your question in the DDK forum so that I can help you there.
Message Edited by Tom W [DE] on 04-09-2008 03:47 PM
Tom W
National Instruments

Register Level DMA programming for NI6533

I am writing a register level driver (LynxOS) for the NI6533. I have the DAQ DIO register map (http://www.ni.com/pdf/daq/us/release_ni6533.pdf) but it does not list registers for the DMA controller chip.
Is there a manual that describes how to setup the DMA registers for this board?
Thanks,
- Larry

Hi Christian,
Thanks for the MITE RLPM, that was the missing piece.
I am now having trouble getting two NI6533's to handshake. One is in a PCI x86 box running LynxOS, and the other is in a desktop PC. For the latter I'm using the Examples:Harware Input and Output:Traditional DAQigital Input and Output:653x examples from LabView 7. Specifically, the Buffered Handshake Output.vi and Cont Handshake Output.vi.
The Cont Handshake Output vi is timing out at 1 second intervals waiting for the write to complete, so I'm assuming from this that no handshaking is occurring.
I can toggle the data lines statically and that looks OK in both directions. I've set the exchangePins bit=1 to swap the ACK/REQ signals on the LynxOS side.
I've attache
d a file that prints the register settings for all of the DIO registers on the LynxOS side. Perhaps you can spot something that's not right?
Also, I'm confused about the delay register settings. The manual states you can adjust the programmable delay from 0 to 700ns in 100ns increments. Yet all of the delay registers show 8-bits. I assume then that only the lower 3 bits are used.
The examples dio_ex12.cpp and dio_ex13.cpp set the group1ReqDelay=3, group1RegNotDelay=2, group1AclDelay=2, and group1AckNotDelay=2, which are consistent with this assumption. However, they set the group1DataDelay=100, which is not consistent. Is this register different than the others?
Thanks,
- Larry
Attachments:
DIO_regs_1.txt ‏7 KB

Batch level settings conversion from plant-to-plant to material-level

If someone has worked on conversion of Batch level settings within SAP from plant-to-plant to material-level batch management, please let me know what are the challenges involved in doing this. Thanks.

Check help !!!
To change the batch level, you have to start a conversion program. This program first checks whether conversion is possible and outputs an error log containing all batch numbers that occur more than once at the new level. Now you need to manually transfer these batch records to batch numbers within Inventory Management using a transfer posting 'material to material'.
If you change the level from plant level to a higher level, it is possible that batches with the same batch numbers in different plants are actually identical. In this case, all you have to do is remove stocks (including previous period stocks) so that all batches with the same batch numbers, except one, can be reorganized.
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Standard settings
In the standard delivery batches are uniquely defined at material level.
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To change the batch level, proceed as follows:
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Further notes
Note that you cannot reset conversion from plant level to a higher level in the standard.
If you create a client by copying an existing client, initially, there are no settings in the target client at batch level. The system makes the settings in the target client only when you have carried out an activity (maintaining master data or posting a goods movement, for example). The client level is not transported. If you copy a client with client level, you have to manually set the client level in the target system.

Content level settings in fact LTS

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Many Thanks,
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Hi,
@Kishore
thank you for quick reply, to get more clarity now lets assume we have one fact table with daily granular data and one aggregate table with month granular data, so when i drag and drop aggregated measures to BMM it creates another LTS for aggregate table, in that aggregate table we would set the content level as "MONTH" so whenever a report is constructed based on month columns and measures, BI Server picks aggregate table since it has LTS at month level. Is my understanding correct?
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2. SALES_AMT
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Please advise database level settings for all our databases for following items:
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Database file growth settings
- And suggest what are the best practices around these items that we need to follow for future new databases. What are different things to consider?
- And also what would we need to do before making these changes on current databases?
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Can you refer the below link
https://www.simple-talk.com/sql/database-administration/sql-server-database-growth-and-autogrowth-settings/
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Register level programing of the 6601 counter to connect signals to the rtsi bus

I have need for more than 4 clocks and have several 6601 counter boards. I would like to use an additional board for the extra clock but need to send signals to the this board from the other. The most efficent way seems to be to use the rtsi bus to connect the 2 boards together. I am programing the counter boards at the register level using a kernel module in linux. The register level porgramming manual explains how to connect different signals to the sourse pins of the clocks including the rtsi signals. I have been successful in doing this but can not find info on how to route the output signal of one clock to the input of another using the rtsi bus. Using web search I have seen ways to do this using labview and dqmx calls but nothing for programin at the register level. Thanks for any help on this problem.
Jerrv

Hi Jerry-
Ed's post here has some info that seems related to your question.
Tom W
National Instruments

6602 register level settings to latch encoder on RTSI trigger

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