74161 RCO ENT cascade issue in multisim

Hi all,
I am building a simulation of an old 70s design based on 74161s and I have had a lot of trouble getting a set of counters to operate according to my expectations.
In my search for understanding more I discovered a recent document that had identified an error in the 74161 multisim model related to the counter executing on falling edge of clock, should be rising edge . Unfortunately it did not solve my headache.
Essentially I have three 74161s in cascade - the RCO for the first counter nicely carries over via ENT to trigger the second counter (ENP is high). But, when the second counter's RCO carries over to the third counters ENT it stays high for a long period of time (the duration of the QA) and sets off the third counter to "race at clock speed" similar to the first counter. When I do the same thing but instead carry over to ENP (having ENT high all the time) the counters work as expected.
The old schematics I use as a base, as well as some cascade counter reading I have come across indicates RCO should connect with ENT and not ENP – then again reading the 74161 datasheet it states that RCO stays high during the duration of QA.
Question to the forum: is the model for 74161 in multsim even more incorrect than the clock edge issue or is my “three cascaded counter” design incorrect? Please find attached the multisim model.
I appreciate any insights.
br /mattias

Hi
Thanks for your reply and apologies for my late return on this.
Please find attached a zip file with the requested information and with updated examples files
* One case where RCO from counter is connected to ENP and one case where RCO from counter is connected to ENT. When connected to ENT (as it appears to be done in the orignal schematics p21, B4 to E4) the third counter starts to race at clock speed when RCO set ENT high (as can be seen in the attached simulation screen shot). This is not the case when connecting to ENP. Something wrong with the 74161 model?
* https://archive.org/download/ArcadeGameManualComputerspace/computerspace.pdf The pdf contains the schematics - see page 21, circuits B4 to E4. They should form a simple 16 bit binary counter that keeps incrementing until all of the output bits for E4 are all zeros and then it loads all the counters with preset value. In the schematics the rco is connected to ENT.
* My test cases (rco to enp and rco to ent) just simulates the circuits B4 to D4 - because it is at D4 where the issue occurs first in the chain (it also occurs at E4 - but not need to simulate; it is the same isse)
Any insight is highly appreciated.

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